1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3*4882a593Smuzhiyun * reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This software is available to you under a choice of one of two
6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the NetLogic
9*4882a593Smuzhiyun * license below:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
12*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
13*4882a593Smuzhiyun * are met:
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * 1. Redistributions of source code must retain the above copyright
16*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
17*4882a593Smuzhiyun * 2. Redistributions in binary form must reproduce the above copyright
18*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
19*4882a593Smuzhiyun * the documentation and/or other materials provided with the
20*4882a593Smuzhiyun * distribution.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23*4882a593Smuzhiyun * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25*4882a593Smuzhiyun * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26*4882a593Smuzhiyun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27*4882a593Smuzhiyun * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28*4882a593Smuzhiyun * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29*4882a593Smuzhiyun * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30*4882a593Smuzhiyun * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31*4882a593Smuzhiyun * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32*4882a593Smuzhiyun * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #ifndef _NLM_HAL_XLP_H
36*4882a593Smuzhiyun #define _NLM_HAL_XLP_H
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define PIC_UART_0_IRQ 17
39*4882a593Smuzhiyun #define PIC_UART_1_IRQ 18
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19
42*4882a593Smuzhiyun #define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i))
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define PIC_EHCI_0_IRQ 23
45*4882a593Smuzhiyun #define PIC_EHCI_1_IRQ 24
46*4882a593Smuzhiyun #define PIC_OHCI_0_IRQ 25
47*4882a593Smuzhiyun #define PIC_OHCI_1_IRQ 26
48*4882a593Smuzhiyun #define PIC_OHCI_2_IRQ 27
49*4882a593Smuzhiyun #define PIC_OHCI_3_IRQ 28
50*4882a593Smuzhiyun #define PIC_2XX_XHCI_0_IRQ 23
51*4882a593Smuzhiyun #define PIC_2XX_XHCI_1_IRQ 24
52*4882a593Smuzhiyun #define PIC_2XX_XHCI_2_IRQ 25
53*4882a593Smuzhiyun #define PIC_9XX_XHCI_0_IRQ 23
54*4882a593Smuzhiyun #define PIC_9XX_XHCI_1_IRQ 24
55*4882a593Smuzhiyun #define PIC_9XX_XHCI_2_IRQ 25
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define PIC_MMC_IRQ 29
58*4882a593Smuzhiyun #define PIC_I2C_0_IRQ 30
59*4882a593Smuzhiyun #define PIC_I2C_1_IRQ 31
60*4882a593Smuzhiyun #define PIC_I2C_2_IRQ 32
61*4882a593Smuzhiyun #define PIC_I2C_3_IRQ 33
62*4882a593Smuzhiyun #define PIC_SPI_IRQ 34
63*4882a593Smuzhiyun #define PIC_NAND_IRQ 37
64*4882a593Smuzhiyun #define PIC_SATA_IRQ 38
65*4882a593Smuzhiyun #define PIC_GPIO_IRQ 39
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */
68*4882a593Smuzhiyun #define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i))
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* MSI-X with second link-level dispatch */
71*4882a593Smuzhiyun #define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
72*4882a593Smuzhiyun #define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
75*4882a593Smuzhiyun #define NLM_MSIX_VEC_BASE 96 /* 96 - 223 - MSIX mapped */
76*4882a593Smuzhiyun #define NLM_MSI_VEC_BASE 224 /* 224 -351 - MSI mapped */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define NLM_PIC_INDIRECT_VEC_BASE 512
79*4882a593Smuzhiyun #define NLM_GPIO_VEC_BASE 768
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define PIC_IRQ_BASE 8
82*4882a593Smuzhiyun #define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
83*4882a593Smuzhiyun #define PIC_IRT_LAST_IRQ 63
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #ifndef __ASSEMBLY__
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* SMP support functions */
88*4882a593Smuzhiyun void xlp_boot_core0_siblings(void);
89*4882a593Smuzhiyun void xlp_wakeup_secondary_cpus(void);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun void xlp_mmu_init(void);
92*4882a593Smuzhiyun void nlm_hal_init(void);
93*4882a593Smuzhiyun int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct pci_dev;
96*4882a593Smuzhiyun int xlp_socdev_to_node(const struct pci_dev *dev);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* Device tree related */
99*4882a593Smuzhiyun void xlp_early_init_devtree(void);
100*4882a593Smuzhiyun void *xlp_dt_init(void *fdtp);
101*4882a593Smuzhiyun
cpu_is_xlpii(void)102*4882a593Smuzhiyun static inline int cpu_is_xlpii(void)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun int chip = read_c0_prid() & PRID_IMP_MASK;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return chip == PRID_IMP_NETLOGIC_XLP2XX ||
107*4882a593Smuzhiyun chip == PRID_IMP_NETLOGIC_XLP9XX ||
108*4882a593Smuzhiyun chip == PRID_IMP_NETLOGIC_XLP5XX;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
cpu_is_xlp9xx(void)111*4882a593Smuzhiyun static inline int cpu_is_xlp9xx(void)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun int chip = read_c0_prid() & PRID_IMP_MASK;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return chip == PRID_IMP_NETLOGIC_XLP9XX ||
116*4882a593Smuzhiyun chip == PRID_IMP_NETLOGIC_XLP5XX;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */
119*4882a593Smuzhiyun #endif /* _ASM_NLM_XLP_H */
120