1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights 3*4882a593Smuzhiyun * reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This software is available to you under a choice of one of two 6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the NetLogic 9*4882a593Smuzhiyun * license below: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 12*4882a593Smuzhiyun * modification, are permitted provided that the following conditions 13*4882a593Smuzhiyun * are met: 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * 1. Redistributions of source code must retain the above copyright 16*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 17*4882a593Smuzhiyun * 2. Redistributions in binary form must reproduce the above copyright 18*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in 19*4882a593Smuzhiyun * the documentation and/or other materials provided with the 20*4882a593Smuzhiyun * distribution. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR 23*4882a593Smuzhiyun * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25*4882a593Smuzhiyun * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE 26*4882a593Smuzhiyun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27*4882a593Smuzhiyun * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28*4882a593Smuzhiyun * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29*4882a593Smuzhiyun * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30*4882a593Smuzhiyun * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31*4882a593Smuzhiyun * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32*4882a593Smuzhiyun * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef __NLM_HAL_BRIDGE_H__ 36*4882a593Smuzhiyun #define __NLM_HAL_BRIDGE_H__ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /** 39*4882a593Smuzhiyun * @file_name mio.h 40*4882a593Smuzhiyun * @author Netlogic Microsystems 41*4882a593Smuzhiyun * @brief Basic definitions of XLP memory and io subsystem 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * BRIDGE specific registers 46*4882a593Smuzhiyun * 47*4882a593Smuzhiyun * These registers start after the PCIe header, which has 0x40 48*4882a593Smuzhiyun * standard entries 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define BRIDGE_MODE 0x00 51*4882a593Smuzhiyun #define BRIDGE_PCI_CFG_BASE 0x01 52*4882a593Smuzhiyun #define BRIDGE_PCI_CFG_LIMIT 0x02 53*4882a593Smuzhiyun #define BRIDGE_PCIE_CFG_BASE 0x03 54*4882a593Smuzhiyun #define BRIDGE_PCIE_CFG_LIMIT 0x04 55*4882a593Smuzhiyun #define BRIDGE_BUSNUM_BAR0 0x05 56*4882a593Smuzhiyun #define BRIDGE_BUSNUM_BAR1 0x06 57*4882a593Smuzhiyun #define BRIDGE_BUSNUM_BAR2 0x07 58*4882a593Smuzhiyun #define BRIDGE_BUSNUM_BAR3 0x08 59*4882a593Smuzhiyun #define BRIDGE_BUSNUM_BAR4 0x09 60*4882a593Smuzhiyun #define BRIDGE_BUSNUM_BAR5 0x0a 61*4882a593Smuzhiyun #define BRIDGE_BUSNUM_BAR6 0x0b 62*4882a593Smuzhiyun #define BRIDGE_FLASH_BAR0 0x0c 63*4882a593Smuzhiyun #define BRIDGE_FLASH_BAR1 0x0d 64*4882a593Smuzhiyun #define BRIDGE_FLASH_BAR2 0x0e 65*4882a593Smuzhiyun #define BRIDGE_FLASH_BAR3 0x0f 66*4882a593Smuzhiyun #define BRIDGE_FLASH_LIMIT0 0x10 67*4882a593Smuzhiyun #define BRIDGE_FLASH_LIMIT1 0x11 68*4882a593Smuzhiyun #define BRIDGE_FLASH_LIMIT2 0x12 69*4882a593Smuzhiyun #define BRIDGE_FLASH_LIMIT3 0x13 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 72*4882a593Smuzhiyun #define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 73*4882a593Smuzhiyun #define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i)) 74*4882a593Smuzhiyun #define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i)) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_BASE0 0x34 77*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_BASE1 0x35 78*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_BASE2 0x36 79*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_BASE3 0x37 80*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_LIMIT0 0x38 81*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_LIMIT1 0x39 82*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_LIMIT2 0x3a 83*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_LIMIT3 0x3b 84*4882a593Smuzhiyun #define BRIDGE_PCIEIO_BASE0 0x3c 85*4882a593Smuzhiyun #define BRIDGE_PCIEIO_BASE1 0x3d 86*4882a593Smuzhiyun #define BRIDGE_PCIEIO_BASE2 0x3e 87*4882a593Smuzhiyun #define BRIDGE_PCIEIO_BASE3 0x3f 88*4882a593Smuzhiyun #define BRIDGE_PCIEIO_LIMIT0 0x40 89*4882a593Smuzhiyun #define BRIDGE_PCIEIO_LIMIT1 0x41 90*4882a593Smuzhiyun #define BRIDGE_PCIEIO_LIMIT2 0x42 91*4882a593Smuzhiyun #define BRIDGE_PCIEIO_LIMIT3 0x43 92*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_BASE4 0x44 93*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_BASE5 0x45 94*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_BASE6 0x46 95*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_LIMIT4 0x47 96*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_LIMIT5 0x48 97*4882a593Smuzhiyun #define BRIDGE_PCIEMEM_LIMIT6 0x49 98*4882a593Smuzhiyun #define BRIDGE_PCIEIO_BASE4 0x4a 99*4882a593Smuzhiyun #define BRIDGE_PCIEIO_BASE5 0x4b 100*4882a593Smuzhiyun #define BRIDGE_PCIEIO_BASE6 0x4c 101*4882a593Smuzhiyun #define BRIDGE_PCIEIO_LIMIT4 0x4d 102*4882a593Smuzhiyun #define BRIDGE_PCIEIO_LIMIT5 0x4e 103*4882a593Smuzhiyun #define BRIDGE_PCIEIO_LIMIT6 0x4f 104*4882a593Smuzhiyun #define BRIDGE_NBU_EVENT_CNT_CTL 0x50 105*4882a593Smuzhiyun #define BRIDGE_EVNTCTR1_LOW 0x51 106*4882a593Smuzhiyun #define BRIDGE_EVNTCTR1_HI 0x52 107*4882a593Smuzhiyun #define BRIDGE_EVNT_CNT_CTL2 0x53 108*4882a593Smuzhiyun #define BRIDGE_EVNTCTR2_LOW 0x54 109*4882a593Smuzhiyun #define BRIDGE_EVNTCTR2_HI 0x55 110*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_MATCH0 0x56 111*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_MATCH1 0x57 112*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_MATCH_LOW 0x58 113*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_MATCH_HI 0x59 114*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_CTRL 0x5a 115*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_INIT 0x5b 116*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_ACCESS 0x5c 117*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_READ_DATA0 0x5d 118*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_READ_DATA1 0x5d 119*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_READ_DATA2 0x5f 120*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_READ_DATA3 0x60 121*4882a593Smuzhiyun #define BRIDGE_TRACEBUF_STATUS 0x61 122*4882a593Smuzhiyun #define BRIDGE_ADDRESS_ERROR0 0x62 123*4882a593Smuzhiyun #define BRIDGE_ADDRESS_ERROR1 0x63 124*4882a593Smuzhiyun #define BRIDGE_ADDRESS_ERROR2 0x64 125*4882a593Smuzhiyun #define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65 126*4882a593Smuzhiyun #define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66 127*4882a593Smuzhiyun #define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67 128*4882a593Smuzhiyun #define BRIDGE_LINE_FLUSH0 0x68 129*4882a593Smuzhiyun #define BRIDGE_LINE_FLUSH1 0x69 130*4882a593Smuzhiyun #define BRIDGE_NODE_ID 0x6a 131*4882a593Smuzhiyun #define BRIDGE_ERROR_INTERRUPT_EN 0x6b 132*4882a593Smuzhiyun #define BRIDGE_PCIE0_WEIGHT 0x2c0 133*4882a593Smuzhiyun #define BRIDGE_PCIE1_WEIGHT 0x2c1 134*4882a593Smuzhiyun #define BRIDGE_PCIE2_WEIGHT 0x2c2 135*4882a593Smuzhiyun #define BRIDGE_PCIE3_WEIGHT 0x2c3 136*4882a593Smuzhiyun #define BRIDGE_USB_WEIGHT 0x2c4 137*4882a593Smuzhiyun #define BRIDGE_NET_WEIGHT 0x2c5 138*4882a593Smuzhiyun #define BRIDGE_POE_WEIGHT 0x2c6 139*4882a593Smuzhiyun #define BRIDGE_CMS_WEIGHT 0x2c7 140*4882a593Smuzhiyun #define BRIDGE_DMAENG_WEIGHT 0x2c8 141*4882a593Smuzhiyun #define BRIDGE_SEC_WEIGHT 0x2c9 142*4882a593Smuzhiyun #define BRIDGE_COMP_WEIGHT 0x2ca 143*4882a593Smuzhiyun #define BRIDGE_GIO_WEIGHT 0x2cb 144*4882a593Smuzhiyun #define BRIDGE_FLASH_WEIGHT 0x2cc 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* FIXME verify */ 147*4882a593Smuzhiyun #define BRIDGE_9XX_FLASH_BAR(i) (0x11 + (i)) 148*4882a593Smuzhiyun #define BRIDGE_9XX_FLASH_BAR_LIMIT(i) (0x15 + (i)) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define BRIDGE_9XX_DRAM_BAR(i) (0x19 + (i)) 151*4882a593Smuzhiyun #define BRIDGE_9XX_DRAM_LIMIT(i) (0x29 + (i)) 152*4882a593Smuzhiyun #define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i)) 153*4882a593Smuzhiyun #define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i)) 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #define BRIDGE_9XX_ADDRESS_ERROR0 0x9d 156*4882a593Smuzhiyun #define BRIDGE_9XX_ADDRESS_ERROR1 0x9e 157*4882a593Smuzhiyun #define BRIDGE_9XX_ADDRESS_ERROR2 0x9f 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEMEM_BASE0 0x59 160*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEMEM_BASE1 0x5a 161*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEMEM_BASE2 0x5b 162*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEMEM_BASE3 0x5c 163*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEMEM_LIMIT0 0x5d 164*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEMEM_LIMIT1 0x5e 165*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEMEM_LIMIT2 0x5f 166*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEMEM_LIMIT3 0x60 167*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEIO_BASE0 0x61 168*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEIO_BASE1 0x62 169*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEIO_BASE2 0x63 170*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEIO_BASE3 0x64 171*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEIO_LIMIT0 0x65 172*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEIO_LIMIT1 0x66 173*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEIO_LIMIT2 0x67 174*4882a593Smuzhiyun #define BRIDGE_9XX_PCIEIO_LIMIT3 0x68 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 179*4882a593Smuzhiyun #define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) 180*4882a593Smuzhiyun #define nlm_get_bridge_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ 181*4882a593Smuzhiyun XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node)) 182*4882a593Smuzhiyun #define nlm_get_bridge_regbase(node) \ 183*4882a593Smuzhiyun (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 186*4882a593Smuzhiyun #endif /* __NLM_HAL_BRIDGE_H__ */ 187