1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * PCI Register definitions for the MIPS System Controller. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 7*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 8*4882a593Smuzhiyun * for more details. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASM_MIPS_BOARDS_MSC01_IC_H 12*4882a593Smuzhiyun #define __ASM_MIPS_BOARDS_MSC01_IC_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /***************************************************************************** 15*4882a593Smuzhiyun * Register offset addresses 16*4882a593Smuzhiyun *****************************************************************************/ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define MSC01_IC_RST_OFS 0x00008 /* Software reset */ 19*4882a593Smuzhiyun #define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */ 20*4882a593Smuzhiyun #define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */ 21*4882a593Smuzhiyun #define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */ 22*4882a593Smuzhiyun #define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */ 23*4882a593Smuzhiyun #define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */ 24*4882a593Smuzhiyun #define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */ 25*4882a593Smuzhiyun #define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */ 26*4882a593Smuzhiyun #define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */ 27*4882a593Smuzhiyun #define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */ 28*4882a593Smuzhiyun #define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */ 29*4882a593Smuzhiyun #define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */ 30*4882a593Smuzhiyun #define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */ 31*4882a593Smuzhiyun #define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */ 32*4882a593Smuzhiyun #define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */ 33*4882a593Smuzhiyun #define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */ 34*4882a593Smuzhiyun #define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */ 35*4882a593Smuzhiyun #define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */ 36*4882a593Smuzhiyun #define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */ 37*4882a593Smuzhiyun #define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */ 38*4882a593Smuzhiyun #define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */ 39*4882a593Smuzhiyun #define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */ 40*4882a593Smuzhiyun #define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */ 41*4882a593Smuzhiyun #define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */ 42*4882a593Smuzhiyun #define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */ 43*4882a593Smuzhiyun #define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /***************************************************************************** 46*4882a593Smuzhiyun * Register field encodings 47*4882a593Smuzhiyun *****************************************************************************/ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define MSC01_IC_RST_RST_SHF 0 50*4882a593Smuzhiyun #define MSC01_IC_RST_RST_MSK 0x00000001 51*4882a593Smuzhiyun #define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK 52*4882a593Smuzhiyun #define MSC01_IC_LVL_LVL_SHF 0 53*4882a593Smuzhiyun #define MSC01_IC_LVL_LVL_MSK 0x000000ff 54*4882a593Smuzhiyun #define MSC01_IC_LVL_SPUR_SHF 16 55*4882a593Smuzhiyun #define MSC01_IC_LVL_SPUR_MSK 0x00010000 56*4882a593Smuzhiyun #define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK 57*4882a593Smuzhiyun #define MSC01_IC_RAMW_RIPL_SHF 0 58*4882a593Smuzhiyun #define MSC01_IC_RAMW_RIPL_MSK 0x0000003f 59*4882a593Smuzhiyun #define MSC01_IC_RAMW_DATA_SHF 6 60*4882a593Smuzhiyun #define MSC01_IC_RAMW_DATA_MSK 0x00000fc0 61*4882a593Smuzhiyun #define MSC01_IC_RAMW_ADDR_SHF 25 62*4882a593Smuzhiyun #define MSC01_IC_RAMW_ADDR_MSK 0x7e000000 63*4882a593Smuzhiyun #define MSC01_IC_RAMW_READ_SHF 31 64*4882a593Smuzhiyun #define MSC01_IC_RAMW_READ_MSK 0x80000000 65*4882a593Smuzhiyun #define MSC01_IC_RAMW_READ_BIT MSC01_IC_RAMW_READ_MSK 66*4882a593Smuzhiyun #define MSC01_IC_OSB_OSB_SHF 0 67*4882a593Smuzhiyun #define MSC01_IC_OSB_OSB_MSK 0x000000ff 68*4882a593Smuzhiyun #define MSC01_IC_OSA_OSA_SHF 0 69*4882a593Smuzhiyun #define MSC01_IC_OSA_OSA_MSK 0x000000ff 70*4882a593Smuzhiyun #define MSC01_IC_GENA_GENA_SHF 0 71*4882a593Smuzhiyun #define MSC01_IC_GENA_GENA_MSK 0x00000001 72*4882a593Smuzhiyun #define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK 73*4882a593Smuzhiyun #define MSC01_IC_CFG_DIS_SHF 0 74*4882a593Smuzhiyun #define MSC01_IC_CFG_DIS_MSK 0x00000001 75*4882a593Smuzhiyun #define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK 76*4882a593Smuzhiyun #define MSC01_IC_CFG_SHFT_SHF 8 77*4882a593Smuzhiyun #define MSC01_IC_CFG_SHFT_MSK 0x00000f00 78*4882a593Smuzhiyun #define MSC01_IC_TCFG_ENA_SHF 0 79*4882a593Smuzhiyun #define MSC01_IC_TCFG_ENA_MSK 0x00000001 80*4882a593Smuzhiyun #define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK 81*4882a593Smuzhiyun #define MSC01_IC_TCFG_INT_SHF 8 82*4882a593Smuzhiyun #define MSC01_IC_TCFG_INT_MSK 0x00000100 83*4882a593Smuzhiyun #define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK 84*4882a593Smuzhiyun #define MSC01_IC_TCFG_EDGE_SHF 16 85*4882a593Smuzhiyun #define MSC01_IC_TCFG_EDGE_MSK 0x00010000 86*4882a593Smuzhiyun #define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK 87*4882a593Smuzhiyun #define MSC01_IC_SUP_PRI_SHF 0 88*4882a593Smuzhiyun #define MSC01_IC_SUP_PRI_MSK 0x00000007 89*4882a593Smuzhiyun #define MSC01_IC_SUP_EDGE_SHF 8 90*4882a593Smuzhiyun #define MSC01_IC_SUP_EDGE_MSK 0x00000100 91*4882a593Smuzhiyun #define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK 92*4882a593Smuzhiyun #define MSC01_IC_SUP_STEP 8 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* 95*4882a593Smuzhiyun * MIPS System controller interrupt register base. 96*4882a593Smuzhiyun * 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /***************************************************************************** 100*4882a593Smuzhiyun * Absolute register addresses 101*4882a593Smuzhiyun *****************************************************************************/ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS) 104*4882a593Smuzhiyun #define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS) 105*4882a593Smuzhiyun #define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS) 106*4882a593Smuzhiyun #define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS) 107*4882a593Smuzhiyun #define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS) 108*4882a593Smuzhiyun #define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS) 109*4882a593Smuzhiyun #define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS) 110*4882a593Smuzhiyun #define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS) 111*4882a593Smuzhiyun #define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS) 112*4882a593Smuzhiyun #define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS) 113*4882a593Smuzhiyun #define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS) 114*4882a593Smuzhiyun #define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS) 115*4882a593Smuzhiyun #define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS) 116*4882a593Smuzhiyun #define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS) 117*4882a593Smuzhiyun #define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS) 118*4882a593Smuzhiyun #define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS) 119*4882a593Smuzhiyun #define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS) 120*4882a593Smuzhiyun #define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS) 121*4882a593Smuzhiyun #define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS) 122*4882a593Smuzhiyun #define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS) 123*4882a593Smuzhiyun #define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS) 124*4882a593Smuzhiyun #define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS) 125*4882a593Smuzhiyun #define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS) 126*4882a593Smuzhiyun #define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS) 127*4882a593Smuzhiyun #define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS) 128*4882a593Smuzhiyun #define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* 131*4882a593Smuzhiyun * Soc-it interrupts are configurable. 132*4882a593Smuzhiyun * Every board describes its IRQ mapping with this table. 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun typedef struct msc_irqmap { 135*4882a593Smuzhiyun int im_irq; 136*4882a593Smuzhiyun int im_type; 137*4882a593Smuzhiyun int im_lvl; 138*4882a593Smuzhiyun } msc_irqmap_t; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* im_type */ 141*4882a593Smuzhiyun #define MSC01_IRQ_LEVEL 0 142*4882a593Smuzhiyun #define MSC01_IRQ_EDGE 1 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq); 145*4882a593Smuzhiyun extern void ll_msc_irq(void); 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */ 148