1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2015 Imagination Technologies, Inc. 7*4882a593Smuzhiyun * written by Ralf Baechle <ralf@linux-mips.org> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ASM_MIPS_BOARDS_SEAD3_ADDR_H 10*4882a593Smuzhiyun #define __ASM_MIPS_BOARDS_SEAD3_ADDR_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Target #0 Register Decode 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define SEAD3_SD_SPDCNF 0xbb000040 16*4882a593Smuzhiyun #define SEAD3_SD_SPADDR 0xbb000048 17*4882a593Smuzhiyun #define SEAD3_SD_DATA 0xbb000050 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * Target #1 Register Decode 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #define SEAD3_CFG 0xbb100110 23*4882a593Smuzhiyun #define SEAD3_GIC_BASE_ADDRESS 0xbb1c0000 24*4882a593Smuzhiyun #define SEAD3_SHARED_SECTION 0xbb1c0000 25*4882a593Smuzhiyun #define SEAD3_VPE_LOCAL_SECTION 0xbb1c8000 26*4882a593Smuzhiyun #define SEAD3_VPE_OTHER_SECTION 0xbb1cc000 27*4882a593Smuzhiyun #define SEAD3_USER_MODE_VISIBLE_SECTION 0xbb1d0000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Target #3 Register Decode 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #define SEAD3_USB_HS_BASE 0xbb200000 33*4882a593Smuzhiyun #define SEAD3_USB_HS_IDENTIFICATION_REGS 0xbb200000 34*4882a593Smuzhiyun #define SEAD3_USB_HS_CAPABILITY_REGS 0xbb200100 35*4882a593Smuzhiyun #define SEAD3_USB_HS_OPERATIONAL_REGS 0xbb200140 36*4882a593Smuzhiyun #define SEAD3_RESERVED 0xbe800000 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Target #3 Register Decode 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define SEAD3_SRAM 0xbe000000 42*4882a593Smuzhiyun #define SEAD3_OPTIONAL_SRAM 0xbe400000 43*4882a593Smuzhiyun #define SEAD3_FPGA 0xbf000000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define SEAD3_PI_PIC32_USB_STATUS 0xbf000060 46*4882a593Smuzhiyun #define SEAD3_PI_PIC32_USB_STATUS_IO_RDY (1 << 0) 47*4882a593Smuzhiyun #define SEAD3_PI_PIC32_USB_STATUS_SPL_INT (1 << 1) 48*4882a593Smuzhiyun #define SEAD3_PI_PIC32_USB_STATUS_GPIOA_INT (1 << 2) 49*4882a593Smuzhiyun #define SEAD3_PI_PIC32_USB_STATUS_GPIOB_INT (1 << 3) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define SEAD3_PI_SOFT_ENDIAN 0xbf000070 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define SEAD3_CPLD_P_SWITCH 0xbf000200 54*4882a593Smuzhiyun #define SEAD3_CPLD_F_SWITCH 0xbf000208 55*4882a593Smuzhiyun #define SEAD3_CPLD_P_LED 0xbf000210 56*4882a593Smuzhiyun #define SEAD3_CPLD_F_LED 0xbf000218 57*4882a593Smuzhiyun #define SEAD3_NEWSC_LIVE 0xbf000220 58*4882a593Smuzhiyun #define SEAD3_NEWSC_REG 0xbf000228 59*4882a593Smuzhiyun #define SEAD3_NEWSC_CTRL 0xbf000230 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define SEAD3_LCD_CONTROL 0xbf000400 62*4882a593Smuzhiyun #define SEAD3_LCD_DATA 0xbf000408 63*4882a593Smuzhiyun #define SEAD3_CPLD_LCD_STATUS 0xbf000410 64*4882a593Smuzhiyun #define SEAD3_CPLD_LCD_DATA 0xbf000418 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define SEAD3_CPLD_PI_DEVRST 0xbf000480 67*4882a593Smuzhiyun #define SEAD3_CPLD_PI_DEVRST_IC32_RST (1 << 0) 68*4882a593Smuzhiyun #define SEAD3_RESERVED_0 0xbf000500 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define SEAD3_PIC32_REGISTERS 0xbf000600 71*4882a593Smuzhiyun #define SEAD3_RESERVED_1 0xbf000700 72*4882a593Smuzhiyun #define SEAD3_UART_CH_0 0xbf000800 73*4882a593Smuzhiyun #define SEAD3_UART_CH_1 0xbf000900 74*4882a593Smuzhiyun #define SEAD3_RESERVED_2 0xbf000a00 75*4882a593Smuzhiyun #define SEAD3_ETHERNET 0xbf010000 76*4882a593Smuzhiyun #define SEAD3_RESERVED_3 0xbf020000 77*4882a593Smuzhiyun #define SEAD3_USER_EXPANSION 0xbf400000 78*4882a593Smuzhiyun #define SEAD3_RESERVED_4 0xbf800000 79*4882a593Smuzhiyun #define SEAD3_BOOT_FLASH_EXTENSION 0xbfa00000 80*4882a593Smuzhiyun #define SEAD3_BOOT_FLASH 0xbfc00000 81*4882a593Smuzhiyun #define SEAD3_REVISION_REGISTER 0xbfc00010 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif /* __ASM_MIPS_BOARDS_SEAD3_ADDR_H */ 84