1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Carsten Langgaard, carstenl@mips.com 4*4882a593Smuzhiyun * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 5*4882a593Smuzhiyun * Copyright (C) 2013 Imagination Technologies Ltd. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Register definitions for Intel PIIX4 South Bridge Device. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ASM_MIPS_BOARDS_PIIX4_H 10*4882a593Smuzhiyun #define __ASM_MIPS_BOARDS_PIIX4_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* PIRQX Route Control */ 13*4882a593Smuzhiyun #define PIIX4_FUNC0_PIRQRC 0x60 14*4882a593Smuzhiyun #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) 15*4882a593Smuzhiyun #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf 16*4882a593Smuzhiyun #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 17*4882a593Smuzhiyun /* SERIRQ Control */ 18*4882a593Smuzhiyun #define PIIX4_FUNC0_SERIRQC 0x64 19*4882a593Smuzhiyun #define PIIX4_FUNC0_SERIRQC_EN (1 << 7) 20*4882a593Smuzhiyun #define PIIX4_FUNC0_SERIRQC_CONT (1 << 6) 21*4882a593Smuzhiyun /* Top Of Memory */ 22*4882a593Smuzhiyun #define PIIX4_FUNC0_TOM 0x69 23*4882a593Smuzhiyun #define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 24*4882a593Smuzhiyun /* Deterministic Latency Control */ 25*4882a593Smuzhiyun #define PIIX4_FUNC0_DLC 0x82 26*4882a593Smuzhiyun #define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) 27*4882a593Smuzhiyun #define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) 28*4882a593Smuzhiyun #define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) 29*4882a593Smuzhiyun /* General Configuration */ 30*4882a593Smuzhiyun #define PIIX4_FUNC0_GENCFG 0xb0 31*4882a593Smuzhiyun #define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* IDE Timing */ 34*4882a593Smuzhiyun #define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40 35*4882a593Smuzhiyun #define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41 36*4882a593Smuzhiyun #define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7) 37*4882a593Smuzhiyun #define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42 38*4882a593Smuzhiyun #define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43 39*4882a593Smuzhiyun #define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Power Management Configuration Space */ 42*4882a593Smuzhiyun #define PIIX4_FUNC3_PMBA 0x40 43*4882a593Smuzhiyun #define PIIX4_FUNC3_PMREGMISC 0x80 44*4882a593Smuzhiyun #define PIIX4_FUNC3_PMREGMISC_EN (1 << 0) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Power Management IO Space */ 47*4882a593Smuzhiyun #define PIIX4_FUNC3IO_PMSTS 0x00 48*4882a593Smuzhiyun #define PIIX4_FUNC3IO_PMSTS_PWRBTN_STS (1 << 8) 49*4882a593Smuzhiyun #define PIIX4_FUNC3IO_PMCNTRL 0x04 50*4882a593Smuzhiyun #define PIIX4_FUNC3IO_PMCNTRL_SUS_EN (1 << 13) 51*4882a593Smuzhiyun #define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP (0x7 << 10) 52*4882a593Smuzhiyun #define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF (0x0 << 10) 53*4882a593Smuzhiyun #define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR (0x1 << 10) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Data for magic special PCI cycle */ 56*4882a593Smuzhiyun #define PIIX4_SUSPEND_MAGIC 0x00120002 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* __ASM_MIPS_BOARDS_PIIX4_H */ 59