1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. 7*4882a593Smuzhiyun * Carsten Langgaard <carstenl@mips.com> 8*4882a593Smuzhiyun * Steven J. Hill <sjhill@mips.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef _MIPS_MALTAINT_H 11*4882a593Smuzhiyun #define _MIPS_MALTAINT_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Interrupts 0..15 are used for Malta ISA compatible interrupts 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define MALTA_INT_BASE 0 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* CPU interrupt offsets */ 19*4882a593Smuzhiyun #define MIPSCPU_INT_SW0 0 20*4882a593Smuzhiyun #define MIPSCPU_INT_SW1 1 21*4882a593Smuzhiyun #define MIPSCPU_INT_MB0 2 22*4882a593Smuzhiyun #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 23*4882a593Smuzhiyun #define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */ 24*4882a593Smuzhiyun #define MIPSCPU_INT_MB1 3 25*4882a593Smuzhiyun #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 26*4882a593Smuzhiyun #define MIPSCPU_INT_MB2 4 27*4882a593Smuzhiyun #define MIPSCPU_INT_MB3 5 28*4882a593Smuzhiyun #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 29*4882a593Smuzhiyun #define MIPSCPU_INT_MB4 6 30*4882a593Smuzhiyun #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * Interrupts 96..127 are used for Soc-it Classic interrupts 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define MSC01C_INT_BASE 96 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* SOC-it Classic interrupt offsets */ 38*4882a593Smuzhiyun #define MSC01C_INT_TMR 0 39*4882a593Smuzhiyun #define MSC01C_INT_PCI 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Interrupts 96..127 are used for Soc-it EIC interrupts 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define MSC01E_INT_BASE 96 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* SOC-it EIC interrupt offsets */ 47*4882a593Smuzhiyun #define MSC01E_INT_SW0 1 48*4882a593Smuzhiyun #define MSC01E_INT_SW1 2 49*4882a593Smuzhiyun #define MSC01E_INT_MB0 3 50*4882a593Smuzhiyun #define MSC01E_INT_I8259A MSC01E_INT_MB0 51*4882a593Smuzhiyun #define MSC01E_INT_MB1 4 52*4882a593Smuzhiyun #define MSC01E_INT_SMI MSC01E_INT_MB1 53*4882a593Smuzhiyun #define MSC01E_INT_MB2 5 54*4882a593Smuzhiyun #define MSC01E_INT_MB3 6 55*4882a593Smuzhiyun #define MSC01E_INT_COREHI MSC01E_INT_MB3 56*4882a593Smuzhiyun #define MSC01E_INT_MB4 7 57*4882a593Smuzhiyun #define MSC01E_INT_CORELO MSC01E_INT_MB4 58*4882a593Smuzhiyun #define MSC01E_INT_TMR 8 59*4882a593Smuzhiyun #define MSC01E_INT_PCI 9 60*4882a593Smuzhiyun #define MSC01E_INT_PERFCTR 10 61*4882a593Smuzhiyun #define MSC01E_INT_CPUCTR 11 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* !(_MIPS_MALTAINT_H) */ 64