1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Defines of the MIPS boards specific address-MAP, registers, etc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2000,2012 MIPS Technologies, Inc. 9*4882a593Smuzhiyun * All rights reserved. 10*4882a593Smuzhiyun * Authors: Carsten Langgaard <carstenl@mips.com> 11*4882a593Smuzhiyun * Steven J. Hill <sjhill@mips.com> 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #ifndef __ASM_MIPS_BOARDS_GENERIC_H 14*4882a593Smuzhiyun #define __ASM_MIPS_BOARDS_GENERIC_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <asm/addrspace.h> 17*4882a593Smuzhiyun #include <asm/byteorder.h> 18*4882a593Smuzhiyun #include <asm/mips-boards/bonito64.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Display register base. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #define ASCII_DISPLAY_WORD_BASE 0x1f000410 24*4882a593Smuzhiyun #define ASCII_DISPLAY_POS_BASE 0x1f000418 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Revision register. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define MIPS_REVISION_REG 0x1fc00010 30*4882a593Smuzhiyun #define MIPS_REVISION_CORID_QED_RM5261 0 31*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_LV 1 32*4882a593Smuzhiyun #define MIPS_REVISION_CORID_BONITO64 2 33*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_20K 3 34*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_FPGA 4 35*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_MSC 5 36*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_EMUL 6 37*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_FPGA2 7 38*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_FPGAR2 8 39*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_FPGA3 9 40*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_24K 10 41*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_FPGA4 11 42*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_FPGA5 12 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /**** Artificial corid defines ****/ 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * CoreEMUL with Bonito System Controller is treated like a Core20K 47*4882a593Smuzhiyun * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_EMUL_BON -1 50*4882a593Smuzhiyun #define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define MIPS_REVISION_SCON_OTHER 0 55*4882a593Smuzhiyun #define MIPS_REVISION_SCON_SOCITSC 1 56*4882a593Smuzhiyun #define MIPS_REVISION_SCON_SOCITSCP 2 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ 59*4882a593Smuzhiyun #define MIPS_REVISION_SCON_UNKNOWN -1 60*4882a593Smuzhiyun #define MIPS_REVISION_SCON_GT64120 -2 61*4882a593Smuzhiyun #define MIPS_REVISION_SCON_BONITO -3 62*4882a593Smuzhiyun #define MIPS_REVISION_SCON_BRTL -4 63*4882a593Smuzhiyun #define MIPS_REVISION_SCON_SOCIT -5 64*4882a593Smuzhiyun #define MIPS_REVISION_SCON_ROCIT -6 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun extern int mips_revision_sconid; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #ifdef CONFIG_PCI 71*4882a593Smuzhiyun extern void mips_pcibios_init(void); 72*4882a593Smuzhiyun #else 73*4882a593Smuzhiyun #define mips_pcibios_init() do { } while (0) 74*4882a593Smuzhiyun #endif 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun extern void mips_scroll_message(void); 77*4882a593Smuzhiyun extern void mips_display_message(const char *str); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 80