1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H 9*4882a593Smuzhiyun #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Sibyte are MIPS64 processors wired to a specific configuration 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define cpu_has_watch 1 15*4882a593Smuzhiyun #define cpu_has_mips16 0 16*4882a593Smuzhiyun #define cpu_has_mips16e2 0 17*4882a593Smuzhiyun #define cpu_has_divec 1 18*4882a593Smuzhiyun #define cpu_has_vce 0 19*4882a593Smuzhiyun #define cpu_has_cache_cdex_p 0 20*4882a593Smuzhiyun #define cpu_has_cache_cdex_s 0 21*4882a593Smuzhiyun #define cpu_has_prefetch 1 22*4882a593Smuzhiyun #define cpu_has_mcheck 1 23*4882a593Smuzhiyun #define cpu_has_ejtag 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define cpu_has_llsc 1 26*4882a593Smuzhiyun #define cpu_has_vtag_icache 1 27*4882a593Smuzhiyun #define cpu_has_dc_aliases 0 28*4882a593Smuzhiyun #define cpu_has_ic_fills_f_dc 0 29*4882a593Smuzhiyun #define cpu_has_dsp 0 30*4882a593Smuzhiyun #define cpu_has_dsp2 0 31*4882a593Smuzhiyun #define cpu_has_mipsmt 0 32*4882a593Smuzhiyun #define cpu_has_userlocal 0 33*4882a593Smuzhiyun #define cpu_icache_snoops_remote_store 0 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define cpu_has_nofpuex 0 36*4882a593Smuzhiyun #define cpu_has_64bits 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define cpu_has_mips32r1 1 39*4882a593Smuzhiyun #define cpu_has_mips32r2 0 40*4882a593Smuzhiyun #define cpu_has_mips64r1 1 41*4882a593Smuzhiyun #define cpu_has_mips64r2 0 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define cpu_has_inclusive_pcaches 0 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define cpu_dcache_line_size() 32 46*4882a593Smuzhiyun #define cpu_icache_line_size() 32 47*4882a593Smuzhiyun #define cpu_scache_line_size() 32 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #endif /* __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H */ 50