1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004 IDT Inc. 5*4882a593Smuzhiyun * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __ASM_RC32434_RB_H 8*4882a593Smuzhiyun #define __ASM_RC32434_RB_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/genhd.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define REGBASE 0x18000000 13*4882a593Smuzhiyun #define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE)) 14*4882a593Smuzhiyun #define UART0BASE 0x58000 15*4882a593Smuzhiyun #define RST (1 << 15) 16*4882a593Smuzhiyun #define DEV0BASE 0x010000 17*4882a593Smuzhiyun #define DEV0MASK 0x010004 18*4882a593Smuzhiyun #define DEV0C 0x010008 19*4882a593Smuzhiyun #define DEV0T 0x01000C 20*4882a593Smuzhiyun #define DEV1BASE 0x010010 21*4882a593Smuzhiyun #define DEV1MASK 0x010014 22*4882a593Smuzhiyun #define DEV1C 0x010018 23*4882a593Smuzhiyun #define DEV1TC 0x01001C 24*4882a593Smuzhiyun #define DEV2BASE 0x010020 25*4882a593Smuzhiyun #define DEV2MASK 0x010024 26*4882a593Smuzhiyun #define DEV2C 0x010028 27*4882a593Smuzhiyun #define DEV2TC 0x01002C 28*4882a593Smuzhiyun #define DEV3BASE 0x010030 29*4882a593Smuzhiyun #define DEV3MASK 0x010034 30*4882a593Smuzhiyun #define DEV3C 0x010038 31*4882a593Smuzhiyun #define DEV3TC 0x01003C 32*4882a593Smuzhiyun #define BTCS 0x010040 33*4882a593Smuzhiyun #define BTCOMPARE 0x010044 34*4882a593Smuzhiyun #define GPIOBASE 0x050000 35*4882a593Smuzhiyun /* Offsets relative to GPIOBASE */ 36*4882a593Smuzhiyun #define GPIOFUNC 0x00 37*4882a593Smuzhiyun #define GPIOCFG 0x04 38*4882a593Smuzhiyun #define GPIOD 0x08 39*4882a593Smuzhiyun #define GPIOILEVEL 0x0C 40*4882a593Smuzhiyun #define GPIOISTAT 0x10 41*4882a593Smuzhiyun #define GPIONMIEN 0x14 42*4882a593Smuzhiyun #define IMASK6 0x38 43*4882a593Smuzhiyun #define LO_WPX (1 << 0) 44*4882a593Smuzhiyun #define LO_ALE (1 << 1) 45*4882a593Smuzhiyun #define LO_CLE (1 << 2) 46*4882a593Smuzhiyun #define LO_CEX (1 << 3) 47*4882a593Smuzhiyun #define LO_FOFF (1 << 5) 48*4882a593Smuzhiyun #define LO_SPICS (1 << 6) 49*4882a593Smuzhiyun #define LO_ULED (1 << 7) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define BIT_TO_MASK(x) (1 << x) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct dev_reg { 54*4882a593Smuzhiyun u32 base; 55*4882a593Smuzhiyun u32 mask; 56*4882a593Smuzhiyun u32 ctl; 57*4882a593Smuzhiyun u32 timing; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct korina_device { 61*4882a593Smuzhiyun char *name; 62*4882a593Smuzhiyun unsigned char mac[6]; 63*4882a593Smuzhiyun struct net_device *dev; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct mpmc_device { 67*4882a593Smuzhiyun unsigned char state; 68*4882a593Smuzhiyun spinlock_t lock; 69*4882a593Smuzhiyun void __iomem *base; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); 73*4882a593Smuzhiyun extern unsigned char get_latch_u5(void); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #endif /* __ASM_RC32434_RB_H */ 76