1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_RC32434_IRQ_H 3*4882a593Smuzhiyun #define __ASM_RC32434_IRQ_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define NR_IRQS 256 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <asm/mach-generic/irq.h> 8*4882a593Smuzhiyun #include <asm/mach-rc32434/rb.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Interrupt Controller */ 11*4882a593Smuzhiyun #define IC_GROUP0_PEND (REGBASE + 0x38000) 12*4882a593Smuzhiyun #define IC_GROUP0_MASK (REGBASE + 0x38008) 13*4882a593Smuzhiyun #define IC_GROUP_OFFSET 0x0C 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define NUM_INTR_GROUPS 5 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 16550 UARTs */ 18*4882a593Smuzhiyun #define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */ 19*4882a593Smuzhiyun /* GRP3 IRQ numbers start here */ 20*4882a593Smuzhiyun #define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) 21*4882a593Smuzhiyun /* GRP4 IRQ numbers start here */ 22*4882a593Smuzhiyun #define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) 23*4882a593Smuzhiyun /* GRP5 IRQ numbers start here */ 24*4882a593Smuzhiyun #define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) 25*4882a593Smuzhiyun #define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define UART0_IRQ (GROUP3_IRQ_BASE + 0) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0) 30*4882a593Smuzhiyun #define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1) 31*4882a593Smuzhiyun #define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) 32*4882a593Smuzhiyun #define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE 35*4882a593Smuzhiyun #define GPIO_MAPPED_IRQ_GROUP 4 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #endif /* __ASM_RC32434_IRQ_H */ 38