1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Definitions for the Watchdog registers 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com> 5*4882a593Smuzhiyun * Copyright 2008 Florian Fainelli <florian@openwrt.org> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 8*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the 9*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your 10*4882a593Smuzhiyun * option) any later version. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13*4882a593Smuzhiyun * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15*4882a593Smuzhiyun * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16*4882a593Smuzhiyun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17*4882a593Smuzhiyun * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18*4882a593Smuzhiyun * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19*4882a593Smuzhiyun * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21*4882a593Smuzhiyun * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along 24*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc., 25*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA. 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #ifndef __RC32434_INTEG_H__ 30*4882a593Smuzhiyun #define __RC32434_INTEG_H__ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #include <asm/mach-rc32434/rb.h> 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define INTEG0_BASE_ADDR 0x18030030 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct integ { 37*4882a593Smuzhiyun u32 errcs; /* sticky use ERRCS_ */ 38*4882a593Smuzhiyun u32 wtcount; /* Watchdog timer count reg. */ 39*4882a593Smuzhiyun u32 wtcompare; /* Watchdog timer timeout value. */ 40*4882a593Smuzhiyun u32 wtc; /* Watchdog timer control. use WTC_ */ 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Error counters */ 44*4882a593Smuzhiyun #define RC32434_ERR_WTO 0 45*4882a593Smuzhiyun #define RC32434_ERR_WNE 1 46*4882a593Smuzhiyun #define RC32434_ERR_UCW 2 47*4882a593Smuzhiyun #define RC32434_ERR_UCR 3 48*4882a593Smuzhiyun #define RC32434_ERR_UPW 4 49*4882a593Smuzhiyun #define RC32434_ERR_UPR 5 50*4882a593Smuzhiyun #define RC32434_ERR_UDW 6 51*4882a593Smuzhiyun #define RC32434_ERR_UDR 7 52*4882a593Smuzhiyun #define RC32434_ERR_SAE 8 53*4882a593Smuzhiyun #define RC32434_ERR_WRE 9 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Watchdog control bits */ 56*4882a593Smuzhiyun #define RC32434_WTC_EN 0 57*4882a593Smuzhiyun #define RC32434_WTC_TO 1 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif /* __RC32434_INTEG_H__ */ 60