1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2002 Integrated Device Technology, Inc.
4*4882a593Smuzhiyun * All rights reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * DMA register definition.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author : ryan.holmQVist@idt.com
9*4882a593Smuzhiyun * Date : 20011005
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef _ASM_RC32434_DMA_V_H_
13*4882a593Smuzhiyun #define _ASM_RC32434_DMA_V_H_
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <asm/mach-rc32434/dma.h>
16*4882a593Smuzhiyun #include <asm/mach-rc32434/rc32434.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define DMA_CHAN_OFFSET 0x14
19*4882a593Smuzhiyun #define IS_DMA_USED(X) (((X) & \
20*4882a593Smuzhiyun (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
21*4882a593Smuzhiyun != 0)
22*4882a593Smuzhiyun #define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define DMA_HALT_TIMEOUT 500
25*4882a593Smuzhiyun
rc32434_halt_dma(struct dma_reg * ch)26*4882a593Smuzhiyun static inline int rc32434_halt_dma(struct dma_reg *ch)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun int timeout = 1;
29*4882a593Smuzhiyun if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
30*4882a593Smuzhiyun __raw_writel(0, &ch->dmac);
31*4882a593Smuzhiyun for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
32*4882a593Smuzhiyun if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
33*4882a593Smuzhiyun __raw_writel(0, &ch->dmas);
34*4882a593Smuzhiyun break;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return timeout ? 0 : 1;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
rc32434_start_dma(struct dma_reg * ch,u32 dma_addr)42*4882a593Smuzhiyun static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun __raw_writel(0, &ch->dmandptr);
45*4882a593Smuzhiyun __raw_writel(dma_addr, &ch->dmadptr);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
rc32434_chain_dma(struct dma_reg * ch,u32 dma_addr)48*4882a593Smuzhiyun static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun __raw_writel(dma_addr, &ch->dmandptr);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #endif /* _ASM_RC32434_DMA_V_H_ */
54