1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2002 Integrated Device Technology, Inc. 4*4882a593Smuzhiyun * All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * DMA register definition. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author : ryan.holmQVist@idt.com 9*4882a593Smuzhiyun * Date : 20011005 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __ASM_RC32434_DMA_H 13*4882a593Smuzhiyun #define __ASM_RC32434_DMA_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/mach-rc32434/rb.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define DMA0_BASE_ADDR 0x18040000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * DMA descriptor (in physical memory). 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct dma_desc { 24*4882a593Smuzhiyun u32 control; /* Control. use DMAD_* */ 25*4882a593Smuzhiyun u32 ca; /* Current Address. */ 26*4882a593Smuzhiyun u32 devcs; /* Device control and status. */ 27*4882a593Smuzhiyun u32 link; /* Next descriptor in chain. */ 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define DMA_DESC_SIZ sizeof(struct dma_desc) 31*4882a593Smuzhiyun #define DMA_DESC_COUNT_BIT 0 32*4882a593Smuzhiyun #define DMA_DESC_COUNT_MSK 0x0003ffff 33*4882a593Smuzhiyun #define DMA_DESC_DS_BIT 20 34*4882a593Smuzhiyun #define DMA_DESC_DS_MSK 0x00300000 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_BIT 22 37*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_MSK 0x01c00000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* DMA command sizes */ 40*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_BYTE 0 41*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_HLF_WD 1 42*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_WORD 2 43*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_2WORDS 3 44*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_4WORDS 4 45*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_6WORDS 5 46*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_8WORDS 6 47*4882a593Smuzhiyun #define DMA_DESC_DEV_CMD_16WORDS 7 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* DMA descriptors interrupts */ 50*4882a593Smuzhiyun #define DMA_DESC_COF (1 << 25) /* Chain on finished */ 51*4882a593Smuzhiyun #define DMA_DESC_COD (1 << 26) /* Chain on done */ 52*4882a593Smuzhiyun #define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */ 53*4882a593Smuzhiyun #define DMA_DESC_IOD (1 << 28) /* Interrupt on done */ 54*4882a593Smuzhiyun #define DMA_DESC_TERM (1 << 29) /* Terminated */ 55*4882a593Smuzhiyun #define DMA_DESC_DONE (1 << 30) /* Done */ 56*4882a593Smuzhiyun #define DMA_DESC_FINI (1 << 31) /* Finished */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * DMA register (within Internal Register Map). 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct dma_reg { 63*4882a593Smuzhiyun u32 dmac; /* Control. */ 64*4882a593Smuzhiyun u32 dmas; /* Status. */ 65*4882a593Smuzhiyun u32 dmasm; /* Mask. */ 66*4882a593Smuzhiyun u32 dmadptr; /* Descriptor pointer. */ 67*4882a593Smuzhiyun u32 dmandptr; /* Next descriptor pointer. */ 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* DMA channels specific registers */ 71*4882a593Smuzhiyun #define DMA_CHAN_RUN_BIT (1 << 0) 72*4882a593Smuzhiyun #define DMA_CHAN_DONE_BIT (1 << 1) 73*4882a593Smuzhiyun #define DMA_CHAN_MODE_BIT (1 << 2) 74*4882a593Smuzhiyun #define DMA_CHAN_MODE_MSK 0x0000000c 75*4882a593Smuzhiyun #define DMA_CHAN_MODE_AUTO 0 76*4882a593Smuzhiyun #define DMA_CHAN_MODE_BURST 1 77*4882a593Smuzhiyun #define DMA_CHAN_MODE_XFRT 2 78*4882a593Smuzhiyun #define DMA_CHAN_MODE_RSVD 3 79*4882a593Smuzhiyun #define DMA_CHAN_ACT_BIT (1 << 4) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* DMA status registers */ 82*4882a593Smuzhiyun #define DMA_STAT_FINI (1 << 0) 83*4882a593Smuzhiyun #define DMA_STAT_DONE (1 << 1) 84*4882a593Smuzhiyun #define DMA_STAT_CHAIN (1 << 2) 85*4882a593Smuzhiyun #define DMA_STAT_ERR (1 << 3) 86*4882a593Smuzhiyun #define DMA_STAT_HALT (1 << 4) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * DMA channel definitions 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define DMA_CHAN_ETH_RCV 0 93*4882a593Smuzhiyun #define DMA_CHAN_ETH_XMT 1 94*4882a593Smuzhiyun #define DMA_CHAN_MEM_TO_FIFO 2 95*4882a593Smuzhiyun #define DMA_CHAN_FIFO_TO_MEM 3 96*4882a593Smuzhiyun #define DMA_CHAN_PCI_TO_MEM 4 97*4882a593Smuzhiyun #define DMA_CHAN_MEM_TO_PCI 5 98*4882a593Smuzhiyun #define DMA_CHAN_COUNT 6 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct dma_channel { 101*4882a593Smuzhiyun struct dma_reg ch[DMA_CHAN_COUNT]; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #endif /* __ASM_RC32434_DMA_H */ 105