1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * IDT RC32434 specific CPU feature overrides 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file was derived from: include/asm-mips/cpu-features.h 8*4882a593Smuzhiyun * Copyright (C) 2003, 2004 Ralf Baechle 9*4882a593Smuzhiyun * Copyright (C) 2004 Maciej W. Rozycki 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H 12*4882a593Smuzhiyun #define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * The IDT RC32434 SOC has a built-in MIPS 4Kc core. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define cpu_has_tlb 1 18*4882a593Smuzhiyun #define cpu_has_4kex 1 19*4882a593Smuzhiyun #define cpu_has_3k_cache 0 20*4882a593Smuzhiyun #define cpu_has_4k_cache 1 21*4882a593Smuzhiyun #define cpu_has_tx39_cache 0 22*4882a593Smuzhiyun #define cpu_has_sb1_cache 0 23*4882a593Smuzhiyun #define cpu_has_fpu 0 24*4882a593Smuzhiyun #define cpu_has_32fpr 0 25*4882a593Smuzhiyun #define cpu_has_counter 1 26*4882a593Smuzhiyun #define cpu_has_watch 1 27*4882a593Smuzhiyun #define cpu_has_divec 1 28*4882a593Smuzhiyun #define cpu_has_vce 0 29*4882a593Smuzhiyun #define cpu_has_cache_cdex_p 0 30*4882a593Smuzhiyun #define cpu_has_cache_cdex_s 0 31*4882a593Smuzhiyun #define cpu_has_prefetch 1 32*4882a593Smuzhiyun #define cpu_has_mcheck 1 33*4882a593Smuzhiyun #define cpu_has_ejtag 1 34*4882a593Smuzhiyun #define cpu_has_llsc 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define cpu_has_mips16 0 37*4882a593Smuzhiyun #define cpu_has_mips16e2 0 38*4882a593Smuzhiyun #define cpu_has_mdmx 0 39*4882a593Smuzhiyun #define cpu_has_mips3d 0 40*4882a593Smuzhiyun #define cpu_has_smartmips 0 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define cpu_has_vtag_icache 0 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define cpu_has_mips32r1 1 45*4882a593Smuzhiyun #define cpu_has_mips32r2 0 46*4882a593Smuzhiyun #define cpu_has_mips64r1 0 47*4882a593Smuzhiyun #define cpu_has_mips64r2 0 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define cpu_has_dsp 0 50*4882a593Smuzhiyun #define cpu_has_dsp2 0 51*4882a593Smuzhiyun #define cpu_has_mipsmt 0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* #define cpu_has_nofpuex ? */ 54*4882a593Smuzhiyun #define cpu_has_64bits 0 55*4882a593Smuzhiyun #define cpu_has_64bit_zero_reg 0 56*4882a593Smuzhiyun #define cpu_has_64bit_gp_regs 0 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define cpu_has_inclusive_pcaches 0 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define cpu_dcache_line_size() 16 61*4882a593Smuzhiyun #define cpu_icache_line_size() 16 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */ 64