1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Ralink RT305x specific CPU feature overrides 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> 6*4882a593Smuzhiyun * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file was derived from: include/asm-mips/cpu-features.h 9*4882a593Smuzhiyun * Copyright (C) 2003, 2004 Ralf Baechle 10*4882a593Smuzhiyun * Copyright (C) 2004 Maciej W. Rozycki 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #ifndef _RT305X_CPU_FEATURE_OVERRIDES_H 13*4882a593Smuzhiyun #define _RT305X_CPU_FEATURE_OVERRIDES_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define cpu_has_tlb 1 16*4882a593Smuzhiyun #define cpu_has_4kex 1 17*4882a593Smuzhiyun #define cpu_has_3k_cache 0 18*4882a593Smuzhiyun #define cpu_has_4k_cache 1 19*4882a593Smuzhiyun #define cpu_has_tx39_cache 0 20*4882a593Smuzhiyun #define cpu_has_sb1_cache 0 21*4882a593Smuzhiyun #define cpu_has_fpu 0 22*4882a593Smuzhiyun #define cpu_has_32fpr 0 23*4882a593Smuzhiyun #define cpu_has_counter 1 24*4882a593Smuzhiyun #define cpu_has_watch 1 25*4882a593Smuzhiyun #define cpu_has_divec 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define cpu_has_prefetch 1 28*4882a593Smuzhiyun #define cpu_has_ejtag 1 29*4882a593Smuzhiyun #define cpu_has_llsc 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define cpu_has_mips16 1 32*4882a593Smuzhiyun #define cpu_has_mdmx 0 33*4882a593Smuzhiyun #define cpu_has_mips3d 0 34*4882a593Smuzhiyun #define cpu_has_smartmips 0 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define cpu_has_mips32r1 1 37*4882a593Smuzhiyun #define cpu_has_mips32r2 1 38*4882a593Smuzhiyun #define cpu_has_mips64r1 0 39*4882a593Smuzhiyun #define cpu_has_mips64r2 0 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define cpu_has_dsp 1 42*4882a593Smuzhiyun #define cpu_has_mipsmt 0 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define cpu_has_64bits 0 45*4882a593Smuzhiyun #define cpu_has_64bit_zero_reg 0 46*4882a593Smuzhiyun #define cpu_has_64bit_gp_regs 0 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define cpu_dcache_line_size() 32 49*4882a593Smuzhiyun #define cpu_icache_line_size() 32 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* _RT305X_CPU_FEATURE_OVERRIDES_H */ 52