1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Parts of this file are based on Ralink's 2.6.21 BSP 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7*4882a593Smuzhiyun * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8*4882a593Smuzhiyun * Copyright (C) 2013 John Crispin <john@phrozen.org> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _RT288X_REGS_H_ 12*4882a593Smuzhiyun #define _RT288X_REGS_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define RT2880_SYSC_BASE 0x00300000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define SYSC_REG_CHIP_NAME0 0x00 17*4882a593Smuzhiyun #define SYSC_REG_CHIP_NAME1 0x04 18*4882a593Smuzhiyun #define SYSC_REG_CHIP_ID 0x0c 19*4882a593Smuzhiyun #define SYSC_REG_SYSTEM_CONFIG 0x10 20*4882a593Smuzhiyun #define SYSC_REG_CLKCFG 0x30 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define RT2880_CHIP_NAME0 0x38325452 23*4882a593Smuzhiyun #define RT2880_CHIP_NAME1 0x20203038 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CHIP_ID_ID_MASK 0xff 26*4882a593Smuzhiyun #define CHIP_ID_ID_SHIFT 8 27*4882a593Smuzhiyun #define CHIP_ID_REV_MASK 0xff 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define SYSTEM_CONFIG_CPUCLK_SHIFT 20 30*4882a593Smuzhiyun #define SYSTEM_CONFIG_CPUCLK_MASK 0x3 31*4882a593Smuzhiyun #define SYSTEM_CONFIG_CPUCLK_250 0x0 32*4882a593Smuzhiyun #define SYSTEM_CONFIG_CPUCLK_266 0x1 33*4882a593Smuzhiyun #define SYSTEM_CONFIG_CPUCLK_280 0x2 34*4882a593Smuzhiyun #define SYSTEM_CONFIG_CPUCLK_300 0x3 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define RT2880_GPIO_MODE_I2C BIT(0) 37*4882a593Smuzhiyun #define RT2880_GPIO_MODE_UART0 BIT(1) 38*4882a593Smuzhiyun #define RT2880_GPIO_MODE_SPI BIT(2) 39*4882a593Smuzhiyun #define RT2880_GPIO_MODE_UART1 BIT(3) 40*4882a593Smuzhiyun #define RT2880_GPIO_MODE_JTAG BIT(4) 41*4882a593Smuzhiyun #define RT2880_GPIO_MODE_MDIO BIT(5) 42*4882a593Smuzhiyun #define RT2880_GPIO_MODE_SDRAM BIT(6) 43*4882a593Smuzhiyun #define RT2880_GPIO_MODE_PCI BIT(7) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CLKCFG_SRAM_CS_N_WDT BIT(9) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define RT2880_SDRAM_BASE 0x08000000 48*4882a593Smuzhiyun #define RT2880_MEM_SIZE_MIN 2 49*4882a593Smuzhiyun #define RT2880_MEM_SIZE_MAX 128 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif 52