1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2015 John Crispin <john@phrozen.org> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _MT7621_REGS_H_ 8*4882a593Smuzhiyun #define _MT7621_REGS_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MT7621_PALMBUS_BASE 0x1C000000 11*4882a593Smuzhiyun #define MT7621_PALMBUS_SIZE 0x03FFFFFF 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define MT7621_SYSC_BASE 0x1E000000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SYSC_REG_CHIP_NAME0 0x00 16*4882a593Smuzhiyun #define SYSC_REG_CHIP_NAME1 0x04 17*4882a593Smuzhiyun #define SYSC_REG_CHIP_REV 0x0c 18*4882a593Smuzhiyun #define SYSC_REG_SYSTEM_CONFIG0 0x10 19*4882a593Smuzhiyun #define SYSC_REG_SYSTEM_CONFIG1 0x14 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CHIP_REV_PKG_MASK 0x1 22*4882a593Smuzhiyun #define CHIP_REV_PKG_SHIFT 16 23*4882a593Smuzhiyun #define CHIP_REV_VER_MASK 0xf 24*4882a593Smuzhiyun #define CHIP_REV_VER_SHIFT 8 25*4882a593Smuzhiyun #define CHIP_REV_ECO_MASK 0xf 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define MT7621_DRAM_BASE 0x0 28*4882a593Smuzhiyun #define MT7621_DDR2_SIZE_MIN 32 29*4882a593Smuzhiyun #define MT7621_DDR2_SIZE_MAX 256 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define MT7621_CHIP_NAME0 0x3637544D 32*4882a593Smuzhiyun #define MT7621_CHIP_NAME1 0x20203132 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif 35