1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Joshua Henderson <joshua.henderson@microchip.com> 4*4882a593Smuzhiyun * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_MACH_PIC32_H 7*4882a593Smuzhiyun #define _ASM_MACH_PIC32_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/io.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * PIC32 register offsets for SET/CLR/INV where supported. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define PIC32_CLR(_reg) ((_reg) + 0x04) 15*4882a593Smuzhiyun #define PIC32_SET(_reg) ((_reg) + 0x08) 16*4882a593Smuzhiyun #define PIC32_INV(_reg) ((_reg) + 0x0C) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * PIC32 Base Register Offsets 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define PIC32_BASE_CONFIG 0x1f800000 22*4882a593Smuzhiyun #define PIC32_BASE_OSC 0x1f801200 23*4882a593Smuzhiyun #define PIC32_BASE_RESET 0x1f801240 24*4882a593Smuzhiyun #define PIC32_BASE_PPS 0x1f801400 25*4882a593Smuzhiyun #define PIC32_BASE_UART 0x1f822000 26*4882a593Smuzhiyun #define PIC32_BASE_PORT 0x1f860000 27*4882a593Smuzhiyun #define PIC32_BASE_DEVCFG2 0x1fc4ff44 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Register unlock sequence required for some register access. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun void pic32_syskey_unlock_debug(const char *fn, const ulong ln); 33*4882a593Smuzhiyun #define pic32_syskey_unlock() \ 34*4882a593Smuzhiyun pic32_syskey_unlock_debug(__func__, __LINE__) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* _ASM_MACH_PIC32_H */ 37