1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ 3*4882a593Smuzhiyun #define _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/cpu-info.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <loongson_regs.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define LOONGSON_FPREV_MASK 0x7 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c); 14*4882a593Smuzhiyun loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips * c)15*4882a593Smuzhiyunstatic inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c) 16*4882a593Smuzhiyun { 17*4882a593Smuzhiyun /* All supported cores have non-zero LOONGSON_CFG1 data. */ 18*4882a593Smuzhiyun return c->loongson3_cpucfg_data[0] != 0; 19*4882a593Smuzhiyun } 20*4882a593Smuzhiyun loongson3_cpucfg_read_synthesized(struct cpuinfo_mips * c,__u64 sel)21*4882a593Smuzhiyunstatic inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c, 22*4882a593Smuzhiyun __u64 sel) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun switch (sel) { 25*4882a593Smuzhiyun case LOONGSON_CFG0: 26*4882a593Smuzhiyun return c->processor_id; 27*4882a593Smuzhiyun case LOONGSON_CFG1: 28*4882a593Smuzhiyun case LOONGSON_CFG2: 29*4882a593Smuzhiyun case LOONGSON_CFG3: 30*4882a593Smuzhiyun return c->loongson3_cpucfg_data[sel - 1]; 31*4882a593Smuzhiyun case LOONGSON_CFG4: 32*4882a593Smuzhiyun case LOONGSON_CFG5: 33*4882a593Smuzhiyun /* CPUCFG selects 4 and 5 are related to the input clock 34*4882a593Smuzhiyun * signal. 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * Unimplemented for now. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun return 0; 39*4882a593Smuzhiyun case LOONGSON_CFG6: 40*4882a593Smuzhiyun /* CPUCFG select 6 is for the undocumented Safe Extension. */ 41*4882a593Smuzhiyun return 0; 42*4882a593Smuzhiyun case LOONGSON_CFG7: 43*4882a593Smuzhiyun /* CPUCFG select 7 is for the virtualization extension. 44*4882a593Smuzhiyun * We don't know if the two currently known features are 45*4882a593Smuzhiyun * supported on older cores according to the public 46*4882a593Smuzhiyun * documentation, so leave this at zero. 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun return 0; 49*4882a593Smuzhiyun } 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Return 0 for unrecognized CPUCFG selects, which is real hardware 53*4882a593Smuzhiyun * behavior observed on Loongson 3A R4. 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun return 0; 56*4882a593Smuzhiyun } 57*4882a593Smuzhiyun #else loongson3_cpucfg_synthesize_data(struct cpuinfo_mips * c)58*4882a593Smuzhiyunstatic inline void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c) 59*4882a593Smuzhiyun { 60*4882a593Smuzhiyun } 61*4882a593Smuzhiyun loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips * c)62*4882a593Smuzhiyunstatic inline bool loongson3_cpucfg_emulation_enabled(struct cpuinfo_mips *c) 63*4882a593Smuzhiyun { 64*4882a593Smuzhiyun return false; 65*4882a593Smuzhiyun } 66*4882a593Smuzhiyun loongson3_cpucfg_read_synthesized(struct cpuinfo_mips * c,__u64 sel)67*4882a593Smuzhiyunstatic inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c, 68*4882a593Smuzhiyun __u64 sel) 69*4882a593Smuzhiyun { 70*4882a593Smuzhiyun return 0; 71*4882a593Smuzhiyun } 72*4882a593Smuzhiyun #endif 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif /* _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ */ 75