1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Loongson 1 PWM Register Definitions. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_MACH_LOONGSON32_REGS_PWM_H 9*4882a593Smuzhiyun #define __ASM_MACH_LOONGSON32_REGS_PWM_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Loongson 1 PWM Timer Register Definitions */ 12*4882a593Smuzhiyun #define PWM_CNT 0x0 13*4882a593Smuzhiyun #define PWM_HRC 0x4 14*4882a593Smuzhiyun #define PWM_LRC 0x8 15*4882a593Smuzhiyun #define PWM_CTRL 0xc 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* PWM Control Register Bits */ 18*4882a593Smuzhiyun #define CNT_RST BIT(7) 19*4882a593Smuzhiyun #define INT_SR BIT(6) 20*4882a593Smuzhiyun #define INT_EN BIT(5) 21*4882a593Smuzhiyun #define PWM_SINGLE BIT(4) 22*4882a593Smuzhiyun #define PWM_OE BIT(3) 23*4882a593Smuzhiyun #define CNT_EN BIT(0) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif /* __ASM_MACH_LOONGSON32_REGS_PWM_H */ 26