1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Loongson 1 Clock Register Definitions. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H 9*4882a593Smuzhiyun #define __ASM_MACH_LOONGSON32_REGS_CLK_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define LS1X_CLK_REG(x) \ 12*4882a593Smuzhiyun ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x))) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) 15*4882a593Smuzhiyun #define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #if defined(CONFIG_LOONGSON1_LS1B) 18*4882a593Smuzhiyun /* Clock PLL Divisor Register Bits */ 19*4882a593Smuzhiyun #define DIV_DC_EN BIT(31) 20*4882a593Smuzhiyun #define DIV_DC_RST BIT(30) 21*4882a593Smuzhiyun #define DIV_CPU_EN BIT(25) 22*4882a593Smuzhiyun #define DIV_CPU_RST BIT(24) 23*4882a593Smuzhiyun #define DIV_DDR_EN BIT(19) 24*4882a593Smuzhiyun #define DIV_DDR_RST BIT(18) 25*4882a593Smuzhiyun #define RST_DC_EN BIT(5) 26*4882a593Smuzhiyun #define RST_DC BIT(4) 27*4882a593Smuzhiyun #define RST_DDR_EN BIT(3) 28*4882a593Smuzhiyun #define RST_DDR BIT(2) 29*4882a593Smuzhiyun #define RST_CPU_EN BIT(1) 30*4882a593Smuzhiyun #define RST_CPU BIT(0) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define DIV_DC_SHIFT 26 33*4882a593Smuzhiyun #define DIV_CPU_SHIFT 20 34*4882a593Smuzhiyun #define DIV_DDR_SHIFT 14 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define DIV_DC_WIDTH 4 37*4882a593Smuzhiyun #define DIV_CPU_WIDTH 4 38*4882a593Smuzhiyun #define DIV_DDR_WIDTH 4 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define BYPASS_DC_SHIFT 12 41*4882a593Smuzhiyun #define BYPASS_DDR_SHIFT 10 42*4882a593Smuzhiyun #define BYPASS_CPU_SHIFT 8 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define BYPASS_DC_WIDTH 1 45*4882a593Smuzhiyun #define BYPASS_DDR_WIDTH 1 46*4882a593Smuzhiyun #define BYPASS_CPU_WIDTH 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #elif defined(CONFIG_LOONGSON1_LS1C) 49*4882a593Smuzhiyun /* PLL/SDRAM Frequency configuration register Bits */ 50*4882a593Smuzhiyun #define PLL_VALID BIT(31) 51*4882a593Smuzhiyun #define FRAC_N GENMASK(23, 16) 52*4882a593Smuzhiyun #define RST_TIME GENMASK(3, 2) 53*4882a593Smuzhiyun #define SDRAM_DIV GENMASK(1, 0) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* CPU/CAMERA/DC Frequency configuration register Bits */ 56*4882a593Smuzhiyun #define DIV_DC_EN BIT(31) 57*4882a593Smuzhiyun #define DIV_DC GENMASK(30, 24) 58*4882a593Smuzhiyun #define DIV_CAM_EN BIT(23) 59*4882a593Smuzhiyun #define DIV_CAM GENMASK(22, 16) 60*4882a593Smuzhiyun #define DIV_CPU_EN BIT(15) 61*4882a593Smuzhiyun #define DIV_CPU GENMASK(14, 8) 62*4882a593Smuzhiyun #define DIV_DC_SEL_EN BIT(5) 63*4882a593Smuzhiyun #define DIV_DC_SEL BIT(4) 64*4882a593Smuzhiyun #define DIV_CAM_SEL_EN BIT(3) 65*4882a593Smuzhiyun #define DIV_CAM_SEL BIT(2) 66*4882a593Smuzhiyun #define DIV_CPU_SEL_EN BIT(1) 67*4882a593Smuzhiyun #define DIV_CPU_SEL BIT(0) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define DIV_DC_SHIFT 24 70*4882a593Smuzhiyun #define DIV_CAM_SHIFT 16 71*4882a593Smuzhiyun #define DIV_CPU_SHIFT 8 72*4882a593Smuzhiyun #define DIV_DDR_SHIFT 0 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define DIV_DC_WIDTH 7 75*4882a593Smuzhiyun #define DIV_CAM_WIDTH 7 76*4882a593Smuzhiyun #define DIV_CPU_WIDTH 7 77*4882a593Smuzhiyun #define DIV_DDR_WIDTH 2 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */ 82