1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Register mappings for Loongson 1 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H 9*4882a593Smuzhiyun #define __ASM_MACH_LOONGSON32_LOONGSON1_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #if defined(CONFIG_LOONGSON1_LS1B) 12*4882a593Smuzhiyun #define DEFAULT_MEMSIZE 64 /* If no memsize provided */ 13*4882a593Smuzhiyun #elif defined(CONFIG_LOONGSON1_LS1C) 14*4882a593Smuzhiyun #define DEFAULT_MEMSIZE 32 15*4882a593Smuzhiyun #endif 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Loongson 1 Register Bases */ 18*4882a593Smuzhiyun #define LS1X_MUX_BASE 0x1fd00420 19*4882a593Smuzhiyun #define LS1X_INTC_BASE 0x1fd01040 20*4882a593Smuzhiyun #define LS1X_GPIO0_BASE 0x1fd010c0 21*4882a593Smuzhiyun #define LS1X_GPIO1_BASE 0x1fd010c4 22*4882a593Smuzhiyun #define LS1X_DMAC_BASE 0x1fd01160 23*4882a593Smuzhiyun #define LS1X_CBUS_BASE 0x1fd011c0 24*4882a593Smuzhiyun #define LS1X_EHCI_BASE 0x1fe00000 25*4882a593Smuzhiyun #define LS1X_OHCI_BASE 0x1fe08000 26*4882a593Smuzhiyun #define LS1X_GMAC0_BASE 0x1fe10000 27*4882a593Smuzhiyun #define LS1X_GMAC1_BASE 0x1fe20000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define LS1X_UART0_BASE 0x1fe40000 30*4882a593Smuzhiyun #define LS1X_UART1_BASE 0x1fe44000 31*4882a593Smuzhiyun #define LS1X_UART2_BASE 0x1fe48000 32*4882a593Smuzhiyun #define LS1X_UART3_BASE 0x1fe4c000 33*4882a593Smuzhiyun #define LS1X_CAN0_BASE 0x1fe50000 34*4882a593Smuzhiyun #define LS1X_CAN1_BASE 0x1fe54000 35*4882a593Smuzhiyun #define LS1X_I2C0_BASE 0x1fe58000 36*4882a593Smuzhiyun #define LS1X_I2C1_BASE 0x1fe68000 37*4882a593Smuzhiyun #define LS1X_I2C2_BASE 0x1fe70000 38*4882a593Smuzhiyun #define LS1X_PWM0_BASE 0x1fe5c000 39*4882a593Smuzhiyun #define LS1X_PWM1_BASE 0x1fe5c010 40*4882a593Smuzhiyun #define LS1X_PWM2_BASE 0x1fe5c020 41*4882a593Smuzhiyun #define LS1X_PWM3_BASE 0x1fe5c030 42*4882a593Smuzhiyun #define LS1X_WDT_BASE 0x1fe5c060 43*4882a593Smuzhiyun #define LS1X_RTC_BASE 0x1fe64000 44*4882a593Smuzhiyun #define LS1X_AC97_BASE 0x1fe74000 45*4882a593Smuzhiyun #define LS1X_NAND_BASE 0x1fe78000 46*4882a593Smuzhiyun #define LS1X_CLK_BASE 0x1fe78030 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #include <regs-clk.h> 49*4882a593Smuzhiyun #include <regs-mux.h> 50*4882a593Smuzhiyun #include <regs-pwm.h> 51*4882a593Smuzhiyun #include <regs-rtc.h> 52*4882a593Smuzhiyun #include <regs-wdt.h> 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */ 55