1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * IRQ mappings for Loongson 1 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ASM_MACH_LOONGSON32_IRQ_H 9*4882a593Smuzhiyun #define __ASM_MACH_LOONGSON32_IRQ_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * CPU core Interrupt Numbers 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define MIPS_CPU_IRQ_BASE 0 15*4882a593Smuzhiyun #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define SOFTINT0_IRQ MIPS_CPU_IRQ(0) 18*4882a593Smuzhiyun #define SOFTINT1_IRQ MIPS_CPU_IRQ(1) 19*4882a593Smuzhiyun #define INT0_IRQ MIPS_CPU_IRQ(2) 20*4882a593Smuzhiyun #define INT1_IRQ MIPS_CPU_IRQ(3) 21*4882a593Smuzhiyun #define INT2_IRQ MIPS_CPU_IRQ(4) 22*4882a593Smuzhiyun #define INT3_IRQ MIPS_CPU_IRQ(5) 23*4882a593Smuzhiyun #define INT4_IRQ MIPS_CPU_IRQ(6) 24*4882a593Smuzhiyun #define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * INT0~3 Interrupt Numbers 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #define LS1X_IRQ_BASE MIPS_CPU_IRQS 32*4882a593Smuzhiyun #define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define LS1X_UART0_IRQ LS1X_IRQ(0, 2) 35*4882a593Smuzhiyun #if defined(CONFIG_LOONGSON1_LS1B) 36*4882a593Smuzhiyun #define LS1X_UART1_IRQ LS1X_IRQ(0, 3) 37*4882a593Smuzhiyun #define LS1X_UART2_IRQ LS1X_IRQ(0, 4) 38*4882a593Smuzhiyun #define LS1X_UART3_IRQ LS1X_IRQ(0, 5) 39*4882a593Smuzhiyun #elif defined(CONFIG_LOONGSON1_LS1C) 40*4882a593Smuzhiyun #define LS1X_UART1_IRQ LS1X_IRQ(0, 4) 41*4882a593Smuzhiyun #define LS1X_UART2_IRQ LS1X_IRQ(0, 5) 42*4882a593Smuzhiyun #endif 43*4882a593Smuzhiyun #define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) 44*4882a593Smuzhiyun #define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) 45*4882a593Smuzhiyun #define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) 46*4882a593Smuzhiyun #define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) 47*4882a593Smuzhiyun #define LS1X_AC97_IRQ LS1X_IRQ(0, 10) 48*4882a593Smuzhiyun #define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) 49*4882a593Smuzhiyun #define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) 50*4882a593Smuzhiyun #define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) 51*4882a593Smuzhiyun #if defined(CONFIG_LOONGSON1_LS1C) 52*4882a593Smuzhiyun #define LS1X_NAND_IRQ LS1X_IRQ(0, 16) 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun #define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) 55*4882a593Smuzhiyun #define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) 56*4882a593Smuzhiyun #define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) 57*4882a593Smuzhiyun #define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) 58*4882a593Smuzhiyun #define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) 59*4882a593Smuzhiyun #define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) 60*4882a593Smuzhiyun #define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) 61*4882a593Smuzhiyun #if defined(CONFIG_LOONGSON1_LS1B) 62*4882a593Smuzhiyun #define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) 63*4882a593Smuzhiyun #define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) 64*4882a593Smuzhiyun #define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) 65*4882a593Smuzhiyun #define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) 66*4882a593Smuzhiyun #define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) 67*4882a593Smuzhiyun #define LS1X_UART4_IRQ LS1X_IRQ(0, 29) 68*4882a593Smuzhiyun #define LS1X_UART5_IRQ LS1X_IRQ(0, 30) 69*4882a593Smuzhiyun #elif defined(CONFIG_LOONGSON1_LS1C) 70*4882a593Smuzhiyun #define LS1X_UART3_IRQ LS1X_IRQ(0, 29) 71*4882a593Smuzhiyun #define LS1X_ADC_IRQ LS1X_IRQ(0, 30) 72*4882a593Smuzhiyun #define LS1X_SDIO_IRQ LS1X_IRQ(0, 31) 73*4882a593Smuzhiyun #endif 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) 76*4882a593Smuzhiyun #define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) 77*4882a593Smuzhiyun #if defined(CONFIG_LOONGSON1_LS1B) 78*4882a593Smuzhiyun #define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) 79*4882a593Smuzhiyun #define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) 80*4882a593Smuzhiyun #elif defined(CONFIG_LOONGSON1_LS1C) 81*4882a593Smuzhiyun #define LS1X_OTG_IRQ LS1X_IRQ(1, 2) 82*4882a593Smuzhiyun #define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3) 83*4882a593Smuzhiyun #define LS1X_CAM_IRQ LS1X_IRQ(1, 4) 84*4882a593Smuzhiyun #define LS1X_UART4_IRQ LS1X_IRQ(1, 5) 85*4882a593Smuzhiyun #define LS1X_UART5_IRQ LS1X_IRQ(1, 6) 86*4882a593Smuzhiyun #define LS1X_UART6_IRQ LS1X_IRQ(1, 7) 87*4882a593Smuzhiyun #define LS1X_UART7_IRQ LS1X_IRQ(1, 8) 88*4882a593Smuzhiyun #define LS1X_UART8_IRQ LS1X_IRQ(1, 9) 89*4882a593Smuzhiyun #define LS1X_UART9_IRQ LS1X_IRQ(1, 13) 90*4882a593Smuzhiyun #define LS1X_UART10_IRQ LS1X_IRQ(1, 14) 91*4882a593Smuzhiyun #define LS1X_UART11_IRQ LS1X_IRQ(1, 15) 92*4882a593Smuzhiyun #define LS1X_I2C0_IRQ LS1X_IRQ(1, 17) 93*4882a593Smuzhiyun #define LS1X_I2C1_IRQ LS1X_IRQ(1, 18) 94*4882a593Smuzhiyun #define LS1X_I2C2_IRQ LS1X_IRQ(1, 19) 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #if defined(CONFIG_LOONGSON1_LS1B) 98*4882a593Smuzhiyun #define INTN 4 99*4882a593Smuzhiyun #elif defined(CONFIG_LOONGSON1_LS1C) 100*4882a593Smuzhiyun #define INTN 5 101*4882a593Smuzhiyun #endif 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #endif /* __ASM_MACH_LOONGSON32_IRQ_H */ 108