1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> 4*4882a593Smuzhiyun * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_MACH_LOONGSON2EF_PCI_H_ 8*4882a593Smuzhiyun #define __ASM_MACH_LOONGSON2EF_PCI_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun extern struct pci_ops loongson_pci_ops; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* this is an offset from mips_io_port_base */ 13*4882a593Smuzhiyun #define LOONGSON_PCI_IO_START 0x00004000UL 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * we use address window2 to map cpu address space to pci space 19*4882a593Smuzhiyun * window2: cpu [1G, 2G] -> pci [1G, 2G] 20*4882a593Smuzhiyun * why not use window 0 & 1? because they are used by cpu when booting. 21*4882a593Smuzhiyun * window0: cpu [0, 256M] -> ddr [0, 256M] 22*4882a593Smuzhiyun * window1: cpu [256M, 512M] -> pci [256M, 512M] 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ 26*4882a593Smuzhiyun #define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ 27*4882a593Smuzhiyun #define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST 30*4882a593Smuzhiyun #define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ 33*4882a593Smuzhiyun LOONGSON_PCI_MEM_START + 1) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #else /* loongson2f/32bit & loongson2e */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* this pci memory space is mapped by pcimap in pci.c */ 38*4882a593Smuzhiyun #define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE 39*4882a593Smuzhiyun #define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* this is an offset from mips_io_port_base */ 42*4882a593Smuzhiyun #define LOONGSON_PCI_IO_START 0x00004000UL 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */ 47