1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2003, 07 Ralf Baechle 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 9*4882a593Smuzhiyun #define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/cpu.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * IP27 only comes with R1x000 family processors, all using the same config 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define cpu_has_tlb 1 17*4882a593Smuzhiyun #define cpu_has_tlbinv 0 18*4882a593Smuzhiyun #define cpu_has_segments 0 19*4882a593Smuzhiyun #define cpu_has_eva 0 20*4882a593Smuzhiyun #define cpu_has_htw 0 21*4882a593Smuzhiyun #define cpu_has_rixiex 0 22*4882a593Smuzhiyun #define cpu_has_maar 0 23*4882a593Smuzhiyun #define cpu_has_rw_llb 0 24*4882a593Smuzhiyun #define cpu_has_3kex 0 25*4882a593Smuzhiyun #define cpu_has_4kex 1 26*4882a593Smuzhiyun #define cpu_has_3k_cache 0 27*4882a593Smuzhiyun #define cpu_has_4k_cache 1 28*4882a593Smuzhiyun #define cpu_has_tx39_cache 0 29*4882a593Smuzhiyun #define cpu_has_nofpuex 0 30*4882a593Smuzhiyun #define cpu_has_32fpr 1 31*4882a593Smuzhiyun #define cpu_has_counter 1 32*4882a593Smuzhiyun #define cpu_has_watch 1 33*4882a593Smuzhiyun #define cpu_has_64bits 1 34*4882a593Smuzhiyun #define cpu_has_divec 0 35*4882a593Smuzhiyun #define cpu_has_vce 0 36*4882a593Smuzhiyun #define cpu_has_cache_cdex_p 0 37*4882a593Smuzhiyun #define cpu_has_cache_cdex_s 0 38*4882a593Smuzhiyun #define cpu_has_prefetch 1 39*4882a593Smuzhiyun #define cpu_has_mcheck 0 40*4882a593Smuzhiyun #define cpu_has_ejtag 0 41*4882a593Smuzhiyun #define cpu_has_llsc 1 42*4882a593Smuzhiyun #define cpu_has_mips16 0 43*4882a593Smuzhiyun #define cpu_has_mips16e2 0 44*4882a593Smuzhiyun #define cpu_has_mdmx 0 45*4882a593Smuzhiyun #define cpu_has_mips3d 0 46*4882a593Smuzhiyun #define cpu_has_smartmips 0 47*4882a593Smuzhiyun #define cpu_has_rixi 0 48*4882a593Smuzhiyun #define cpu_has_xpa 0 49*4882a593Smuzhiyun #define cpu_has_vtag_icache 0 50*4882a593Smuzhiyun #define cpu_has_dc_aliases 0 51*4882a593Smuzhiyun #define cpu_has_ic_fills_f_dc 0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define cpu_icache_snoops_remote_store 1 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define cpu_has_mips32r1 0 56*4882a593Smuzhiyun #define cpu_has_mips32r2 0 57*4882a593Smuzhiyun #define cpu_has_mips64r1 0 58*4882a593Smuzhiyun #define cpu_has_mips64r2 0 59*4882a593Smuzhiyun #define cpu_has_mips32r6 0 60*4882a593Smuzhiyun #define cpu_has_mips64r6 0 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define cpu_has_dsp 0 63*4882a593Smuzhiyun #define cpu_has_dsp2 0 64*4882a593Smuzhiyun #define cpu_has_mipsmt 0 65*4882a593Smuzhiyun #define cpu_has_userlocal 0 66*4882a593Smuzhiyun #define cpu_has_inclusive_pcaches 1 67*4882a593Smuzhiyun #define cpu_has_perf_cntr_intr_bit 0 68*4882a593Smuzhiyun #define cpu_has_vz 0 69*4882a593Smuzhiyun #define cpu_has_fre 0 70*4882a593Smuzhiyun #define cpu_has_cdmm 0 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define cpu_dcache_line_size() 32 73*4882a593Smuzhiyun #define cpu_icache_line_size() 64 74*4882a593Smuzhiyun #define cpu_scache_line_size() 128 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */ 77