1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * CPU feature overrides for DECstation systems. Two variations 4*4882a593Smuzhiyun * are generally applicable. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2013 Maciej W. Rozycki 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H 9*4882a593Smuzhiyun #define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Generic ones first. */ 12*4882a593Smuzhiyun #define cpu_has_tlb 1 13*4882a593Smuzhiyun #define cpu_has_tlbinv 0 14*4882a593Smuzhiyun #define cpu_has_segments 0 15*4882a593Smuzhiyun #define cpu_has_eva 0 16*4882a593Smuzhiyun #define cpu_has_htw 0 17*4882a593Smuzhiyun #define cpu_has_rixiex 0 18*4882a593Smuzhiyun #define cpu_has_maar 0 19*4882a593Smuzhiyun #define cpu_has_rw_llb 0 20*4882a593Smuzhiyun #define cpu_has_tx39_cache 0 21*4882a593Smuzhiyun #define cpu_has_divec 0 22*4882a593Smuzhiyun #define cpu_has_prefetch 0 23*4882a593Smuzhiyun #define cpu_has_mcheck 0 24*4882a593Smuzhiyun #define cpu_has_ejtag 0 25*4882a593Smuzhiyun #define cpu_has_mips16 0 26*4882a593Smuzhiyun #define cpu_has_mips16e2 0 27*4882a593Smuzhiyun #define cpu_has_mdmx 0 28*4882a593Smuzhiyun #define cpu_has_mips3d 0 29*4882a593Smuzhiyun #define cpu_has_smartmips 0 30*4882a593Smuzhiyun #define cpu_has_rixi 0 31*4882a593Smuzhiyun #define cpu_has_xpa 0 32*4882a593Smuzhiyun #define cpu_has_vtag_icache 0 33*4882a593Smuzhiyun #define cpu_has_ic_fills_f_dc 0 34*4882a593Smuzhiyun #define cpu_has_pindexed_dcache 0 35*4882a593Smuzhiyun #define cpu_icache_snoops_remote_store 1 36*4882a593Smuzhiyun #define cpu_has_mips_4 0 37*4882a593Smuzhiyun #define cpu_has_mips_5 0 38*4882a593Smuzhiyun #define cpu_has_mips32r1 0 39*4882a593Smuzhiyun #define cpu_has_mips32r2 0 40*4882a593Smuzhiyun #define cpu_has_mips64r1 0 41*4882a593Smuzhiyun #define cpu_has_mips64r2 0 42*4882a593Smuzhiyun #define cpu_has_dsp 0 43*4882a593Smuzhiyun #define cpu_has_dsp2 0 44*4882a593Smuzhiyun #define cpu_has_mipsmt 0 45*4882a593Smuzhiyun #define cpu_has_userlocal 0 46*4882a593Smuzhiyun #define cpu_has_perf_cntr_intr_bit 0 47*4882a593Smuzhiyun #define cpu_has_vz 0 48*4882a593Smuzhiyun #define cpu_has_fre 0 49*4882a593Smuzhiyun #define cpu_has_cdmm 0 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* R3k-specific ones. */ 52*4882a593Smuzhiyun #ifdef CONFIG_CPU_R3000 53*4882a593Smuzhiyun #define cpu_has_3kex 1 54*4882a593Smuzhiyun #define cpu_has_4kex 0 55*4882a593Smuzhiyun #define cpu_has_3k_cache 1 56*4882a593Smuzhiyun #define cpu_has_4k_cache 0 57*4882a593Smuzhiyun #define cpu_has_32fpr 0 58*4882a593Smuzhiyun #define cpu_has_counter 0 59*4882a593Smuzhiyun #define cpu_has_watch 0 60*4882a593Smuzhiyun #define cpu_has_vce 0 61*4882a593Smuzhiyun #define cpu_has_cache_cdex_p 0 62*4882a593Smuzhiyun #define cpu_has_cache_cdex_s 0 63*4882a593Smuzhiyun #define cpu_has_llsc 0 64*4882a593Smuzhiyun #define cpu_has_dc_aliases 0 65*4882a593Smuzhiyun #define cpu_has_mips_2 0 66*4882a593Smuzhiyun #define cpu_has_mips_3 0 67*4882a593Smuzhiyun #define cpu_has_nofpuex 1 68*4882a593Smuzhiyun #define cpu_has_inclusive_pcaches 0 69*4882a593Smuzhiyun #define cpu_dcache_line_size() 4 70*4882a593Smuzhiyun #define cpu_icache_line_size() 4 71*4882a593Smuzhiyun #define cpu_scache_line_size() 0 72*4882a593Smuzhiyun #endif /* CONFIG_CPU_R3000 */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* R4k-specific ones. */ 75*4882a593Smuzhiyun #ifdef CONFIG_CPU_R4X00 76*4882a593Smuzhiyun #define cpu_has_3kex 0 77*4882a593Smuzhiyun #define cpu_has_4kex 1 78*4882a593Smuzhiyun #define cpu_has_3k_cache 0 79*4882a593Smuzhiyun #define cpu_has_4k_cache 1 80*4882a593Smuzhiyun #define cpu_has_32fpr 1 81*4882a593Smuzhiyun #define cpu_has_counter 1 82*4882a593Smuzhiyun #define cpu_has_watch 1 83*4882a593Smuzhiyun #define cpu_has_vce 1 84*4882a593Smuzhiyun #define cpu_has_cache_cdex_p 1 85*4882a593Smuzhiyun #define cpu_has_cache_cdex_s 1 86*4882a593Smuzhiyun #define cpu_has_llsc 1 87*4882a593Smuzhiyun #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) 88*4882a593Smuzhiyun #define cpu_has_mips_2 1 89*4882a593Smuzhiyun #define cpu_has_mips_3 1 90*4882a593Smuzhiyun #define cpu_has_nofpuex 0 91*4882a593Smuzhiyun #define cpu_has_inclusive_pcaches 1 92*4882a593Smuzhiyun #define cpu_dcache_line_size() 16 93*4882a593Smuzhiyun #define cpu_icache_line_size() 16 94*4882a593Smuzhiyun #define cpu_scache_line_size() 32 95*4882a593Smuzhiyun #endif /* CONFIG_CPU_R4X00 */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */ 98