1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Cobalt IRQ definitions. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 5*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 6*4882a593Smuzhiyun * for more details. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 1997 Cobalt Microserver 9*4882a593Smuzhiyun * Copyright (C) 1997, 2003 Ralf Baechle 10*4882a593Smuzhiyun * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) 11*4882a593Smuzhiyun * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #ifndef _ASM_COBALT_IRQ_H 14*4882a593Smuzhiyun #define _ASM_COBALT_IRQ_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * i8259 interrupts used on Cobalt: 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * 8 - RTC 20*4882a593Smuzhiyun * 9 - PCI slot 21*4882a593Smuzhiyun * 14 - IDE0 22*4882a593Smuzhiyun * 15 - IDE1(no connector on board) 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define I8259A_IRQ_BASE 0 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * CPU interrupts used on Cobalt: 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * 0 - Software interrupt 0 (unused) 32*4882a593Smuzhiyun * 1 - Software interrupt 0 (unused) 33*4882a593Smuzhiyun * 2 - cascade GT64111 34*4882a593Smuzhiyun * 3 - ethernet or SCSI host controller 35*4882a593Smuzhiyun * 4 - ethernet 36*4882a593Smuzhiyun * 5 - 16550 UART 37*4882a593Smuzhiyun * 6 - cascade i8259 38*4882a593Smuzhiyun * 7 - CP0 counter 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define MIPS_CPU_IRQ_BASE 16 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) 43*4882a593Smuzhiyun #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) 44*4882a593Smuzhiyun #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) 45*4882a593Smuzhiyun #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) 46*4882a593Smuzhiyun #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) 47*4882a593Smuzhiyun #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) 48*4882a593Smuzhiyun #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) 49*4882a593Smuzhiyun #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define GT641XX_IRQ_BASE 24 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #include <asm/irq_gt641xx.h> 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif /* _ASM_COBALT_IRQ_H */ 58