1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2004-2008 Cavium Networks 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __OCTEON_IRQ_H__ 9*4882a593Smuzhiyun #define __OCTEON_IRQ_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define NR_IRQS OCTEON_IRQ_LAST 12*4882a593Smuzhiyun #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun enum octeon_irq { 15*4882a593Smuzhiyun /* 1 - 8 represent the 8 MIPS standard interrupt sources */ 16*4882a593Smuzhiyun OCTEON_IRQ_SW0 = 1, 17*4882a593Smuzhiyun OCTEON_IRQ_SW1, 18*4882a593Smuzhiyun /* CIU0, CUI2, CIU4 are 3, 4, 5 */ 19*4882a593Smuzhiyun OCTEON_IRQ_5 = 6, 20*4882a593Smuzhiyun OCTEON_IRQ_PERF, 21*4882a593Smuzhiyun OCTEON_IRQ_TIMER, 22*4882a593Smuzhiyun /* sources in CIU_INTX_EN0 */ 23*4882a593Smuzhiyun OCTEON_IRQ_WORKQ0, 24*4882a593Smuzhiyun OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64, 25*4882a593Smuzhiyun OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32, 26*4882a593Smuzhiyun OCTEON_IRQ_MBOX1, 27*4882a593Smuzhiyun OCTEON_IRQ_MBOX2, 28*4882a593Smuzhiyun OCTEON_IRQ_MBOX3, 29*4882a593Smuzhiyun OCTEON_IRQ_PCI_INT0, 30*4882a593Smuzhiyun OCTEON_IRQ_PCI_INT1, 31*4882a593Smuzhiyun OCTEON_IRQ_PCI_INT2, 32*4882a593Smuzhiyun OCTEON_IRQ_PCI_INT3, 33*4882a593Smuzhiyun OCTEON_IRQ_PCI_MSI0, 34*4882a593Smuzhiyun OCTEON_IRQ_PCI_MSI1, 35*4882a593Smuzhiyun OCTEON_IRQ_PCI_MSI2, 36*4882a593Smuzhiyun OCTEON_IRQ_PCI_MSI3, 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun OCTEON_IRQ_TWSI, 39*4882a593Smuzhiyun OCTEON_IRQ_TWSI2, 40*4882a593Smuzhiyun OCTEON_IRQ_RML, 41*4882a593Smuzhiyun OCTEON_IRQ_TIMER0, 42*4882a593Smuzhiyun OCTEON_IRQ_TIMER1, 43*4882a593Smuzhiyun OCTEON_IRQ_TIMER2, 44*4882a593Smuzhiyun OCTEON_IRQ_TIMER3, 45*4882a593Smuzhiyun #ifndef CONFIG_PCI_MSI 46*4882a593Smuzhiyun OCTEON_IRQ_LAST = 127 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #ifdef CONFIG_PCI_MSI 51*4882a593Smuzhiyun /* 256 - 511 represent the MSI interrupts 0-255 */ 52*4882a593Smuzhiyun #define OCTEON_IRQ_MSI_BIT0 (256) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) 55*4882a593Smuzhiyun #define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) 56*4882a593Smuzhiyun #endif 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif 59