1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef BCM63XX_IOREMAP_H_ 3*4882a593Smuzhiyun #define BCM63XX_IOREMAP_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <bcm63xx_cpu.h> 6*4882a593Smuzhiyun is_bcm63xx_internal_registers(phys_addr_t offset)7*4882a593Smuzhiyunstatic inline int is_bcm63xx_internal_registers(phys_addr_t offset) 8*4882a593Smuzhiyun { 9*4882a593Smuzhiyun switch (bcm63xx_get_cpu_id()) { 10*4882a593Smuzhiyun case BCM3368_CPU_ID: 11*4882a593Smuzhiyun if (offset >= 0xfff80000) 12*4882a593Smuzhiyun return 1; 13*4882a593Smuzhiyun break; 14*4882a593Smuzhiyun case BCM6338_CPU_ID: 15*4882a593Smuzhiyun case BCM6345_CPU_ID: 16*4882a593Smuzhiyun case BCM6348_CPU_ID: 17*4882a593Smuzhiyun case BCM6358_CPU_ID: 18*4882a593Smuzhiyun if (offset >= 0xfff00000) 19*4882a593Smuzhiyun return 1; 20*4882a593Smuzhiyun break; 21*4882a593Smuzhiyun case BCM6328_CPU_ID: 22*4882a593Smuzhiyun case BCM6362_CPU_ID: 23*4882a593Smuzhiyun case BCM6368_CPU_ID: 24*4882a593Smuzhiyun if (offset >= 0xb0000000 && offset < 0xb1000000) 25*4882a593Smuzhiyun return 1; 26*4882a593Smuzhiyun break; 27*4882a593Smuzhiyun } 28*4882a593Smuzhiyun return 0; 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun plat_ioremap(phys_addr_t offset,unsigned long size,unsigned long flags)31*4882a593Smuzhiyunstatic inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, 32*4882a593Smuzhiyun unsigned long flags) 33*4882a593Smuzhiyun { 34*4882a593Smuzhiyun if (is_bcm63xx_internal_registers(offset)) 35*4882a593Smuzhiyun return (void __iomem *)offset; 36*4882a593Smuzhiyun return NULL; 37*4882a593Smuzhiyun } 38*4882a593Smuzhiyun plat_iounmap(const volatile void __iomem * addr)39*4882a593Smuzhiyunstatic inline int plat_iounmap(const volatile void __iomem *addr) 40*4882a593Smuzhiyun { 41*4882a593Smuzhiyun return is_bcm63xx_internal_registers((unsigned long)addr); 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif /* BCM63XX_IOREMAP_H_ */ 45