1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _GPIO_AU1300_H_ 9*4882a593Smuzhiyun #define _GPIO_AU1300_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/addrspace.h> 12*4882a593Smuzhiyun #include <asm/io.h> 13*4882a593Smuzhiyun #include <asm/mach-au1x00/au1000.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct gpio; 16*4882a593Smuzhiyun struct gpio_chip; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* with the current GPIC design, up to 128 GPIOs are possible. 19*4882a593Smuzhiyun * The only implementation so far is in the Au1300, which has 75 externally 20*4882a593Smuzhiyun * available GPIOs. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #define AU1300_GPIO_BASE 0 23*4882a593Smuzhiyun #define AU1300_GPIO_NUM 75 24*4882a593Smuzhiyun #define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define AU1300_GPIC_ADDR \ 27*4882a593Smuzhiyun (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR) 28*4882a593Smuzhiyun au1300_gpio_get_value(unsigned int gpio)29*4882a593Smuzhiyunstatic inline int au1300_gpio_get_value(unsigned int gpio) 30*4882a593Smuzhiyun { 31*4882a593Smuzhiyun void __iomem *roff = AU1300_GPIC_ADDR; 32*4882a593Smuzhiyun int bit; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun gpio -= AU1300_GPIO_BASE; 35*4882a593Smuzhiyun roff += GPIC_GPIO_BANKOFF(gpio); 36*4882a593Smuzhiyun bit = GPIC_GPIO_TO_BIT(gpio); 37*4882a593Smuzhiyun return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; 38*4882a593Smuzhiyun } 39*4882a593Smuzhiyun au1300_gpio_direction_input(unsigned int gpio)40*4882a593Smuzhiyunstatic inline int au1300_gpio_direction_input(unsigned int gpio) 41*4882a593Smuzhiyun { 42*4882a593Smuzhiyun void __iomem *roff = AU1300_GPIC_ADDR; 43*4882a593Smuzhiyun unsigned long bit; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun gpio -= AU1300_GPIO_BASE; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun roff += GPIC_GPIO_BANKOFF(gpio); 48*4882a593Smuzhiyun bit = GPIC_GPIO_TO_BIT(gpio); 49*4882a593Smuzhiyun __raw_writel(bit, roff + AU1300_GPIC_DEVCLR); 50*4882a593Smuzhiyun wmb(); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun return 0; 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun au1300_gpio_set_value(unsigned int gpio,int v)55*4882a593Smuzhiyunstatic inline int au1300_gpio_set_value(unsigned int gpio, int v) 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun void __iomem *roff = AU1300_GPIC_ADDR; 58*4882a593Smuzhiyun unsigned long bit; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun gpio -= AU1300_GPIO_BASE; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun roff += GPIC_GPIO_BANKOFF(gpio); 63*4882a593Smuzhiyun bit = GPIC_GPIO_TO_BIT(gpio); 64*4882a593Smuzhiyun __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL 65*4882a593Smuzhiyun : AU1300_GPIC_PINVALCLR)); 66*4882a593Smuzhiyun wmb(); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun return 0; 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun au1300_gpio_direction_output(unsigned int gpio,int v)71*4882a593Smuzhiyunstatic inline int au1300_gpio_direction_output(unsigned int gpio, int v) 72*4882a593Smuzhiyun { 73*4882a593Smuzhiyun /* hw switches to output automatically */ 74*4882a593Smuzhiyun return au1300_gpio_set_value(gpio, v); 75*4882a593Smuzhiyun } 76*4882a593Smuzhiyun au1300_gpio_to_irq(unsigned int gpio)77*4882a593Smuzhiyunstatic inline int au1300_gpio_to_irq(unsigned int gpio) 78*4882a593Smuzhiyun { 79*4882a593Smuzhiyun return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE); 80*4882a593Smuzhiyun } 81*4882a593Smuzhiyun au1300_irq_to_gpio(unsigned int irq)82*4882a593Smuzhiyunstatic inline int au1300_irq_to_gpio(unsigned int irq) 83*4882a593Smuzhiyun { 84*4882a593Smuzhiyun return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE; 85*4882a593Smuzhiyun } 86*4882a593Smuzhiyun au1300_gpio_is_valid(unsigned int gpio)87*4882a593Smuzhiyunstatic inline int au1300_gpio_is_valid(unsigned int gpio) 88*4882a593Smuzhiyun { 89*4882a593Smuzhiyun int ret; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun switch (alchemy_get_cputype()) { 92*4882a593Smuzhiyun case ALCHEMY_CPU_AU1300: 93*4882a593Smuzhiyun ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX)); 94*4882a593Smuzhiyun break; 95*4882a593Smuzhiyun default: 96*4882a593Smuzhiyun ret = 0; 97*4882a593Smuzhiyun } 98*4882a593Smuzhiyun return ret; 99*4882a593Smuzhiyun } 100*4882a593Smuzhiyun au1300_gpio_cansleep(unsigned int gpio)101*4882a593Smuzhiyunstatic inline int au1300_gpio_cansleep(unsigned int gpio) 102*4882a593Smuzhiyun { 103*4882a593Smuzhiyun return 0; 104*4882a593Smuzhiyun } 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* hardware remembers gpio 0-63 levels on powerup */ au1300_gpio_getinitlvl(unsigned int gpio)107*4882a593Smuzhiyunstatic inline int au1300_gpio_getinitlvl(unsigned int gpio) 108*4882a593Smuzhiyun { 109*4882a593Smuzhiyun void __iomem *roff = AU1300_GPIC_ADDR; 110*4882a593Smuzhiyun unsigned long v; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun if (unlikely(gpio > 63)) 113*4882a593Smuzhiyun return 0; 114*4882a593Smuzhiyun else if (gpio > 31) { 115*4882a593Smuzhiyun gpio -= 32; 116*4882a593Smuzhiyun roff += 4; 117*4882a593Smuzhiyun } 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun v = __raw_readl(roff + AU1300_GPIC_RSTVAL); 120*4882a593Smuzhiyun return (v >> gpio) & 1; 121*4882a593Smuzhiyun } 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif /* _GPIO_AU1300_H_ */ 124