1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Atheros AR933X UART defines 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __AR933X_UART_H 9*4882a593Smuzhiyun #define __AR933X_UART_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define AR933X_UART_REGS_SIZE 20 12*4882a593Smuzhiyun #define AR933X_UART_FIFO_SIZE 16 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define AR933X_UART_DATA_REG 0x00 15*4882a593Smuzhiyun #define AR933X_UART_CS_REG 0x04 16*4882a593Smuzhiyun #define AR933X_UART_CLOCK_REG 0x08 17*4882a593Smuzhiyun #define AR933X_UART_INT_REG 0x0c 18*4882a593Smuzhiyun #define AR933X_UART_INT_EN_REG 0x10 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AR933X_UART_DATA_TX_RX_MASK 0xff 21*4882a593Smuzhiyun #define AR933X_UART_DATA_RX_CSR BIT(8) 22*4882a593Smuzhiyun #define AR933X_UART_DATA_TX_CSR BIT(9) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define AR933X_UART_CS_PARITY_S 0 25*4882a593Smuzhiyun #define AR933X_UART_CS_PARITY_M 0x3 26*4882a593Smuzhiyun #define AR933X_UART_CS_PARITY_NONE 0 27*4882a593Smuzhiyun #define AR933X_UART_CS_PARITY_ODD 2 28*4882a593Smuzhiyun #define AR933X_UART_CS_PARITY_EVEN 3 29*4882a593Smuzhiyun #define AR933X_UART_CS_IF_MODE_S 2 30*4882a593Smuzhiyun #define AR933X_UART_CS_IF_MODE_M 0x3 31*4882a593Smuzhiyun #define AR933X_UART_CS_IF_MODE_NONE 0 32*4882a593Smuzhiyun #define AR933X_UART_CS_IF_MODE_DTE 1 33*4882a593Smuzhiyun #define AR933X_UART_CS_IF_MODE_DCE 2 34*4882a593Smuzhiyun #define AR933X_UART_CS_FLOW_CTRL_S 4 35*4882a593Smuzhiyun #define AR933X_UART_CS_FLOW_CTRL_M 0x3 36*4882a593Smuzhiyun #define AR933X_UART_CS_DMA_EN BIT(6) 37*4882a593Smuzhiyun #define AR933X_UART_CS_TX_READY_ORIDE BIT(7) 38*4882a593Smuzhiyun #define AR933X_UART_CS_RX_READY_ORIDE BIT(8) 39*4882a593Smuzhiyun #define AR933X_UART_CS_TX_READY BIT(9) 40*4882a593Smuzhiyun #define AR933X_UART_CS_RX_BREAK BIT(10) 41*4882a593Smuzhiyun #define AR933X_UART_CS_TX_BREAK BIT(11) 42*4882a593Smuzhiyun #define AR933X_UART_CS_HOST_INT BIT(12) 43*4882a593Smuzhiyun #define AR933X_UART_CS_HOST_INT_EN BIT(13) 44*4882a593Smuzhiyun #define AR933X_UART_CS_TX_BUSY BIT(14) 45*4882a593Smuzhiyun #define AR933X_UART_CS_RX_BUSY BIT(15) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define AR933X_UART_CLOCK_STEP_M 0xffff 48*4882a593Smuzhiyun #define AR933X_UART_CLOCK_SCALE_M 0xfff 49*4882a593Smuzhiyun #define AR933X_UART_CLOCK_SCALE_S 16 50*4882a593Smuzhiyun #define AR933X_UART_CLOCK_STEP_M 0xffff 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define AR933X_UART_INT_RX_VALID BIT(0) 53*4882a593Smuzhiyun #define AR933X_UART_INT_TX_READY BIT(1) 54*4882a593Smuzhiyun #define AR933X_UART_INT_RX_FRAMING_ERR BIT(2) 55*4882a593Smuzhiyun #define AR933X_UART_INT_RX_OFLOW_ERR BIT(3) 56*4882a593Smuzhiyun #define AR933X_UART_INT_TX_OFLOW_ERR BIT(4) 57*4882a593Smuzhiyun #define AR933X_UART_INT_RX_PARITY_ERR BIT(5) 58*4882a593Smuzhiyun #define AR933X_UART_INT_RX_BREAK_ON BIT(6) 59*4882a593Smuzhiyun #define AR933X_UART_INT_RX_BREAK_OFF BIT(7) 60*4882a593Smuzhiyun #define AR933X_UART_INT_RX_FULL BIT(8) 61*4882a593Smuzhiyun #define AR933X_UART_INT_TX_EMPTY BIT(9) 62*4882a593Smuzhiyun #define AR933X_UART_INT_ALLINTS 0x3ff 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __AR933X_UART_H */ 65