1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Atheros AR231x/AR531x SoC specific CPU feature overrides 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file was derived from: include/asm-mips/cpu-features.h 8*4882a593Smuzhiyun * Copyright (C) 2003, 2004 Ralf Baechle 9*4882a593Smuzhiyun * Copyright (C) 2004 Maciej W. Rozycki 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H 12*4882a593Smuzhiyun #define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define cpu_has_tlb 1 18*4882a593Smuzhiyun #define cpu_has_4kex 1 19*4882a593Smuzhiyun #define cpu_has_3k_cache 0 20*4882a593Smuzhiyun #define cpu_has_4k_cache 1 21*4882a593Smuzhiyun #define cpu_has_tx39_cache 0 22*4882a593Smuzhiyun #define cpu_has_sb1_cache 0 23*4882a593Smuzhiyun #define cpu_has_fpu 0 24*4882a593Smuzhiyun #define cpu_has_32fpr 0 25*4882a593Smuzhiyun #define cpu_has_counter 1 26*4882a593Smuzhiyun #define cpu_has_ejtag 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #if !defined(CONFIG_SOC_AR5312) 29*4882a593Smuzhiyun # define cpu_has_llsc 1 30*4882a593Smuzhiyun #else 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the 33*4882a593Smuzhiyun * ll/sc instructions. 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun # define cpu_has_llsc 0 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define cpu_has_mips16 0 39*4882a593Smuzhiyun #define cpu_has_mips16e2 0 40*4882a593Smuzhiyun #define cpu_has_mdmx 0 41*4882a593Smuzhiyun #define cpu_has_mips3d 0 42*4882a593Smuzhiyun #define cpu_has_smartmips 0 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define cpu_has_mips32r1 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #if !defined(CONFIG_SOC_AR5312) 47*4882a593Smuzhiyun # define cpu_has_mips32r2 1 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define cpu_has_mips64r1 0 51*4882a593Smuzhiyun #define cpu_has_mips64r2 0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define cpu_has_dsp 0 54*4882a593Smuzhiyun #define cpu_has_mipsmt 0 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define cpu_has_64bits 0 57*4882a593Smuzhiyun #define cpu_has_64bit_zero_reg 0 58*4882a593Smuzhiyun #define cpu_has_64bit_gp_regs 0 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */ 61