1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2014 Imagination Technologies
4*4882a593Smuzhiyun * Author: Paul Burton <paul.burton@mips.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __MIPS_ASM_MIPS_MAAR_H__
8*4882a593Smuzhiyun #define __MIPS_ASM_MIPS_MAAR_H__
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <asm/hazards.h>
11*4882a593Smuzhiyun #include <asm/mipsregs.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /**
14*4882a593Smuzhiyun * platform_maar_init() - perform platform-level MAAR configuration
15*4882a593Smuzhiyun * @num_pairs: The number of MAAR pairs present in the system.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * Platforms should implement this function such that it configures as many
18*4882a593Smuzhiyun * MAAR pairs as required, from 0 up to the maximum of num_pairs-1, and returns
19*4882a593Smuzhiyun * the number that were used. Any further MAARs will be configured to be
20*4882a593Smuzhiyun * invalid. The default implementation of this function will simply indicate
21*4882a593Smuzhiyun * that it has configured 0 MAAR pairs.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Return: The number of MAAR pairs configured.
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun unsigned platform_maar_init(unsigned num_pairs);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /**
28*4882a593Smuzhiyun * write_maar_pair() - write to a pair of MAARs
29*4882a593Smuzhiyun * @idx: The index of the pair (ie. use MAARs idx*2 & (idx*2)+1).
30*4882a593Smuzhiyun * @lower: The lowest address that the MAAR pair will affect. Must be
31*4882a593Smuzhiyun * aligned to a 2^16 byte boundary.
32*4882a593Smuzhiyun * @upper: The highest address that the MAAR pair will affect. Must be
33*4882a593Smuzhiyun * aligned to one byte before a 2^16 byte boundary.
34*4882a593Smuzhiyun * @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
35*4882a593Smuzhiyun * MIPS_MAAR_VL/MIPS_MAAR_VH attributes will automatically be set.
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * Program the pair of MAAR registers specified by idx to apply the attributes
38*4882a593Smuzhiyun * specified by attrs to the range of addresses from lower to higher.
39*4882a593Smuzhiyun */
write_maar_pair(unsigned idx,phys_addr_t lower,phys_addr_t upper,unsigned attrs)40*4882a593Smuzhiyun static inline void write_maar_pair(unsigned idx, phys_addr_t lower,
41*4882a593Smuzhiyun phys_addr_t upper, unsigned attrs)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun /* Addresses begin at bit 16, but are shifted right 4 bits */
44*4882a593Smuzhiyun BUG_ON(lower & (0xffff | ~(MIPS_MAAR_ADDR << 4)));
45*4882a593Smuzhiyun BUG_ON(((upper & 0xffff) != 0xffff)
46*4882a593Smuzhiyun || ((upper & ~0xffffull) & ~(MIPS_MAAR_ADDR << 4)));
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Automatically set MIPS_MAAR_VL */
49*4882a593Smuzhiyun attrs |= MIPS_MAAR_VL;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * Write the upper address & attributes (both MIPS_MAAR_VL and
53*4882a593Smuzhiyun * MIPS_MAAR_VH matter)
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun write_c0_maari(idx << 1);
56*4882a593Smuzhiyun back_to_back_c0_hazard();
57*4882a593Smuzhiyun write_c0_maar(((upper >> 4) & MIPS_MAAR_ADDR) | attrs);
58*4882a593Smuzhiyun back_to_back_c0_hazard();
59*4882a593Smuzhiyun #ifdef CONFIG_XPA
60*4882a593Smuzhiyun upper >>= MIPS_MAARX_ADDR_SHIFT;
61*4882a593Smuzhiyun writex_c0_maar(((upper >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
62*4882a593Smuzhiyun back_to_back_c0_hazard();
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Write the lower address & attributes */
66*4882a593Smuzhiyun write_c0_maari((idx << 1) | 0x1);
67*4882a593Smuzhiyun back_to_back_c0_hazard();
68*4882a593Smuzhiyun write_c0_maar((lower >> 4) | attrs);
69*4882a593Smuzhiyun back_to_back_c0_hazard();
70*4882a593Smuzhiyun #ifdef CONFIG_XPA
71*4882a593Smuzhiyun lower >>= MIPS_MAARX_ADDR_SHIFT;
72*4882a593Smuzhiyun writex_c0_maar(((lower >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH);
73*4882a593Smuzhiyun back_to_back_c0_hazard();
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /**
78*4882a593Smuzhiyun * maar_init() - initialise MAARs
79*4882a593Smuzhiyun *
80*4882a593Smuzhiyun * Performs initialisation of MAARs for the current CPU, making use of the
81*4882a593Smuzhiyun * platforms implementation of platform_maar_init where necessary and
82*4882a593Smuzhiyun * duplicating the setup it provides on secondary CPUs.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun extern void maar_init(void);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /**
87*4882a593Smuzhiyun * struct maar_config - MAAR configuration data
88*4882a593Smuzhiyun * @lower: The lowest address that the MAAR pair will affect. Must be
89*4882a593Smuzhiyun * aligned to a 2^16 byte boundary.
90*4882a593Smuzhiyun * @upper: The highest address that the MAAR pair will affect. Must be
91*4882a593Smuzhiyun * aligned to one byte before a 2^16 byte boundary.
92*4882a593Smuzhiyun * @attrs: The accessibility attributes to program, eg. MIPS_MAAR_S. The
93*4882a593Smuzhiyun * MIPS_MAAR_VL attribute will automatically be set.
94*4882a593Smuzhiyun *
95*4882a593Smuzhiyun * Describes the configuration of a pair of Memory Accessibility Attribute
96*4882a593Smuzhiyun * Registers - applying attributes from attrs to the range of physical
97*4882a593Smuzhiyun * addresses from lower to upper inclusive.
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun struct maar_config {
100*4882a593Smuzhiyun phys_addr_t lower;
101*4882a593Smuzhiyun phys_addr_t upper;
102*4882a593Smuzhiyun unsigned attrs;
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /**
106*4882a593Smuzhiyun * maar_config() - configure MAARs according to provided data
107*4882a593Smuzhiyun * @cfg: Pointer to an array of struct maar_config.
108*4882a593Smuzhiyun * @num_cfg: The number of structs in the cfg array.
109*4882a593Smuzhiyun * @num_pairs: The number of MAAR pairs present in the system.
110*4882a593Smuzhiyun *
111*4882a593Smuzhiyun * Configures as many MAARs as are present and specified in the cfg
112*4882a593Smuzhiyun * array with the values taken from the cfg array.
113*4882a593Smuzhiyun *
114*4882a593Smuzhiyun * Return: The number of MAAR pairs configured.
115*4882a593Smuzhiyun */
maar_config(const struct maar_config * cfg,unsigned num_cfg,unsigned num_pairs)116*4882a593Smuzhiyun static inline unsigned maar_config(const struct maar_config *cfg,
117*4882a593Smuzhiyun unsigned num_cfg, unsigned num_pairs)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun unsigned i;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun for (i = 0; i < min(num_cfg, num_pairs); i++)
122*4882a593Smuzhiyun write_maar_pair(i, cfg[i].lower, cfg[i].upper, cfg[i].attrs);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return i;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #endif /* __MIPS_ASM_MIPS_MAAR_H__ */
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