1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _ASM_JAZZDMA_H 6*4882a593Smuzhiyun #define _ASM_JAZZDMA_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * Prototypes and macros 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size); 12*4882a593Smuzhiyun extern int vdma_free(unsigned long laddr); 13*4882a593Smuzhiyun extern unsigned long vdma_phys2log(unsigned long paddr); 14*4882a593Smuzhiyun extern unsigned long vdma_log2phys(unsigned long laddr); 15*4882a593Smuzhiyun extern void vdma_stats(void); /* for debugging only */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun extern void vdma_enable(int channel); 18*4882a593Smuzhiyun extern void vdma_disable(int channel); 19*4882a593Smuzhiyun extern void vdma_set_mode(int channel, int mode); 20*4882a593Smuzhiyun extern void vdma_set_addr(int channel, long addr); 21*4882a593Smuzhiyun extern void vdma_set_count(int channel, int count); 22*4882a593Smuzhiyun extern int vdma_get_residue(int channel); 23*4882a593Smuzhiyun extern int vdma_get_enable(int channel); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * some definitions used by the driver functions 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define VDMA_PAGESIZE 4096 29*4882a593Smuzhiyun #define VDMA_PGTBL_ENTRIES 4096 30*4882a593Smuzhiyun #define VDMA_PGTBL_SIZE (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES) 31*4882a593Smuzhiyun #define VDMA_PAGE_EMPTY 0xff000000 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Macros to get page no. and offset of a given address 35*4882a593Smuzhiyun * Note that VDMA_PAGE() works for physical addresses only 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define VDMA_PAGE(a) ((unsigned int)(a) >> 12) 38*4882a593Smuzhiyun #define VDMA_OFFSET(a) ((unsigned int)(a) & (VDMA_PAGESIZE-1)) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * VDMA pagetable entry description 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun typedef volatile struct VDMA_PGTBL_ENTRY { 44*4882a593Smuzhiyun unsigned int frame; /* physical frame no. */ 45*4882a593Smuzhiyun unsigned int owner; /* owner of this entry (0=free) */ 46*4882a593Smuzhiyun } VDMA_PGTBL_ENTRY; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * DMA channel control registers 51*4882a593Smuzhiyun * in the R4030 MCT_ADR chip 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #define JAZZ_R4030_CHNL_MODE 0xE0000100 /* 8 DMA Channel Mode Registers, */ 54*4882a593Smuzhiyun /* 0xE0000100,120,140... */ 55*4882a593Smuzhiyun #define JAZZ_R4030_CHNL_ENABLE 0xE0000108 /* 8 DMA Channel Enable Regs, */ 56*4882a593Smuzhiyun /* 0xE0000108,128,148... */ 57*4882a593Smuzhiyun #define JAZZ_R4030_CHNL_COUNT 0xE0000110 /* 8 DMA Channel Byte Cnt Regs, */ 58*4882a593Smuzhiyun /* 0xE0000110,130,150... */ 59*4882a593Smuzhiyun #define JAZZ_R4030_CHNL_ADDR 0xE0000118 /* 8 DMA Channel Address Regs, */ 60*4882a593Smuzhiyun /* 0xE0000118,138,158... */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* channel enable register bits */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define R4030_CHNL_ENABLE (1<<0) 65*4882a593Smuzhiyun #define R4030_CHNL_WRITE (1<<1) 66*4882a593Smuzhiyun #define R4030_TC_INTR (1<<8) 67*4882a593Smuzhiyun #define R4030_MEM_INTR (1<<9) 68*4882a593Smuzhiyun #define R4030_ADDR_INTR (1<<10) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * Channel mode register bits 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #define R4030_MODE_ATIME_40 (0) /* device access time on remote bus */ 74*4882a593Smuzhiyun #define R4030_MODE_ATIME_80 (1) 75*4882a593Smuzhiyun #define R4030_MODE_ATIME_120 (2) 76*4882a593Smuzhiyun #define R4030_MODE_ATIME_160 (3) 77*4882a593Smuzhiyun #define R4030_MODE_ATIME_200 (4) 78*4882a593Smuzhiyun #define R4030_MODE_ATIME_240 (5) 79*4882a593Smuzhiyun #define R4030_MODE_ATIME_280 (6) 80*4882a593Smuzhiyun #define R4030_MODE_ATIME_320 (7) 81*4882a593Smuzhiyun #define R4030_MODE_WIDTH_8 (1<<3) /* device data bus width */ 82*4882a593Smuzhiyun #define R4030_MODE_WIDTH_16 (2<<3) 83*4882a593Smuzhiyun #define R4030_MODE_WIDTH_32 (3<<3) 84*4882a593Smuzhiyun #define R4030_MODE_INTR_EN (1<<5) 85*4882a593Smuzhiyun #define R4030_MODE_BURST (1<<6) /* Rev. 2 only */ 86*4882a593Smuzhiyun #define R4030_MODE_FAST_ACK (1<<7) /* Rev. 2 only */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif /* _ASM_JAZZDMA_H */ 89