1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Galileo/Marvell GT641xx IRQ definitions. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _ASM_IRQ_GT641XX_H 8*4882a593Smuzhiyun #define _ASM_IRQ_GT641XX_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef GT641XX_IRQ_BASE 11*4882a593Smuzhiyun #define GT641XX_IRQ_BASE 8 12*4882a593Smuzhiyun #endif 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1) 15*4882a593Smuzhiyun #define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2) 16*4882a593Smuzhiyun #define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3) 17*4882a593Smuzhiyun #define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4) 18*4882a593Smuzhiyun #define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5) 19*4882a593Smuzhiyun #define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6) 20*4882a593Smuzhiyun #define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7) 21*4882a593Smuzhiyun #define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8) 22*4882a593Smuzhiyun #define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9) 23*4882a593Smuzhiyun #define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10) 24*4882a593Smuzhiyun #define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11) 25*4882a593Smuzhiyun #define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12) 26*4882a593Smuzhiyun #define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13) 27*4882a593Smuzhiyun #define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14) 28*4882a593Smuzhiyun #define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15) 29*4882a593Smuzhiyun #define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16) 30*4882a593Smuzhiyun #define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17) 31*4882a593Smuzhiyun #define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18) 32*4882a593Smuzhiyun #define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19) 33*4882a593Smuzhiyun #define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20) 34*4882a593Smuzhiyun #define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21) 35*4882a593Smuzhiyun #define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22) 36*4882a593Smuzhiyun #define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23) 37*4882a593Smuzhiyun #define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24) 38*4882a593Smuzhiyun #define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25) 39*4882a593Smuzhiyun #define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26) 40*4882a593Smuzhiyun #define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27) 41*4882a593Smuzhiyun #define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28) 42*4882a593Smuzhiyun #define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun extern void gt641xx_irq_dispatch(void); 45*4882a593Smuzhiyun extern void gt641xx_irq_init(void); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif /* _ASM_IRQ_GT641XX_H */ 48