1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Further private data for which no space exists in mips_fpu_struct.
5*4882a593Smuzhiyun * This should be subsumed into the mips_fpu_struct structure as
6*4882a593Smuzhiyun * defined in processor.h as soon as the absurd wired absolute assembler
7*4882a593Smuzhiyun * offsets become dynamic at compile time.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10*4882a593Smuzhiyun * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #ifndef _ASM_FPU_EMULATOR_H
13*4882a593Smuzhiyun #define _ASM_FPU_EMULATOR_H
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/sched.h>
16*4882a593Smuzhiyun #include <asm/dsemul.h>
17*4882a593Smuzhiyun #include <asm/thread_info.h>
18*4882a593Smuzhiyun #include <asm/inst.h>
19*4882a593Smuzhiyun #include <asm/local.h>
20*4882a593Smuzhiyun #include <asm/processor.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct mips_fpu_emulator_stats {
25*4882a593Smuzhiyun unsigned long emulated;
26*4882a593Smuzhiyun unsigned long loads;
27*4882a593Smuzhiyun unsigned long stores;
28*4882a593Smuzhiyun unsigned long branches;
29*4882a593Smuzhiyun unsigned long cp1ops;
30*4882a593Smuzhiyun unsigned long cp1xops;
31*4882a593Smuzhiyun unsigned long errors;
32*4882a593Smuzhiyun unsigned long ieee754_inexact;
33*4882a593Smuzhiyun unsigned long ieee754_underflow;
34*4882a593Smuzhiyun unsigned long ieee754_overflow;
35*4882a593Smuzhiyun unsigned long ieee754_zerodiv;
36*4882a593Smuzhiyun unsigned long ieee754_invalidop;
37*4882a593Smuzhiyun unsigned long ds_emul;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun unsigned long abs_s;
40*4882a593Smuzhiyun unsigned long abs_d;
41*4882a593Smuzhiyun unsigned long add_s;
42*4882a593Smuzhiyun unsigned long add_d;
43*4882a593Smuzhiyun unsigned long bc1eqz;
44*4882a593Smuzhiyun unsigned long bc1nez;
45*4882a593Smuzhiyun unsigned long ceil_w_s;
46*4882a593Smuzhiyun unsigned long ceil_w_d;
47*4882a593Smuzhiyun unsigned long ceil_l_s;
48*4882a593Smuzhiyun unsigned long ceil_l_d;
49*4882a593Smuzhiyun unsigned long class_s;
50*4882a593Smuzhiyun unsigned long class_d;
51*4882a593Smuzhiyun unsigned long cmp_af_s;
52*4882a593Smuzhiyun unsigned long cmp_af_d;
53*4882a593Smuzhiyun unsigned long cmp_eq_s;
54*4882a593Smuzhiyun unsigned long cmp_eq_d;
55*4882a593Smuzhiyun unsigned long cmp_le_s;
56*4882a593Smuzhiyun unsigned long cmp_le_d;
57*4882a593Smuzhiyun unsigned long cmp_lt_s;
58*4882a593Smuzhiyun unsigned long cmp_lt_d;
59*4882a593Smuzhiyun unsigned long cmp_ne_s;
60*4882a593Smuzhiyun unsigned long cmp_ne_d;
61*4882a593Smuzhiyun unsigned long cmp_or_s;
62*4882a593Smuzhiyun unsigned long cmp_or_d;
63*4882a593Smuzhiyun unsigned long cmp_ueq_s;
64*4882a593Smuzhiyun unsigned long cmp_ueq_d;
65*4882a593Smuzhiyun unsigned long cmp_ule_s;
66*4882a593Smuzhiyun unsigned long cmp_ule_d;
67*4882a593Smuzhiyun unsigned long cmp_ult_s;
68*4882a593Smuzhiyun unsigned long cmp_ult_d;
69*4882a593Smuzhiyun unsigned long cmp_un_s;
70*4882a593Smuzhiyun unsigned long cmp_un_d;
71*4882a593Smuzhiyun unsigned long cmp_une_s;
72*4882a593Smuzhiyun unsigned long cmp_une_d;
73*4882a593Smuzhiyun unsigned long cmp_saf_s;
74*4882a593Smuzhiyun unsigned long cmp_saf_d;
75*4882a593Smuzhiyun unsigned long cmp_seq_s;
76*4882a593Smuzhiyun unsigned long cmp_seq_d;
77*4882a593Smuzhiyun unsigned long cmp_sle_s;
78*4882a593Smuzhiyun unsigned long cmp_sle_d;
79*4882a593Smuzhiyun unsigned long cmp_slt_s;
80*4882a593Smuzhiyun unsigned long cmp_slt_d;
81*4882a593Smuzhiyun unsigned long cmp_sne_s;
82*4882a593Smuzhiyun unsigned long cmp_sne_d;
83*4882a593Smuzhiyun unsigned long cmp_sor_s;
84*4882a593Smuzhiyun unsigned long cmp_sor_d;
85*4882a593Smuzhiyun unsigned long cmp_sueq_s;
86*4882a593Smuzhiyun unsigned long cmp_sueq_d;
87*4882a593Smuzhiyun unsigned long cmp_sule_s;
88*4882a593Smuzhiyun unsigned long cmp_sule_d;
89*4882a593Smuzhiyun unsigned long cmp_sult_s;
90*4882a593Smuzhiyun unsigned long cmp_sult_d;
91*4882a593Smuzhiyun unsigned long cmp_sun_s;
92*4882a593Smuzhiyun unsigned long cmp_sun_d;
93*4882a593Smuzhiyun unsigned long cmp_sune_s;
94*4882a593Smuzhiyun unsigned long cmp_sune_d;
95*4882a593Smuzhiyun unsigned long cvt_d_l;
96*4882a593Smuzhiyun unsigned long cvt_d_s;
97*4882a593Smuzhiyun unsigned long cvt_d_w;
98*4882a593Smuzhiyun unsigned long cvt_l_s;
99*4882a593Smuzhiyun unsigned long cvt_l_d;
100*4882a593Smuzhiyun unsigned long cvt_s_d;
101*4882a593Smuzhiyun unsigned long cvt_s_l;
102*4882a593Smuzhiyun unsigned long cvt_s_w;
103*4882a593Smuzhiyun unsigned long cvt_w_s;
104*4882a593Smuzhiyun unsigned long cvt_w_d;
105*4882a593Smuzhiyun unsigned long div_s;
106*4882a593Smuzhiyun unsigned long div_d;
107*4882a593Smuzhiyun unsigned long floor_w_s;
108*4882a593Smuzhiyun unsigned long floor_w_d;
109*4882a593Smuzhiyun unsigned long floor_l_s;
110*4882a593Smuzhiyun unsigned long floor_l_d;
111*4882a593Smuzhiyun unsigned long maddf_s;
112*4882a593Smuzhiyun unsigned long maddf_d;
113*4882a593Smuzhiyun unsigned long max_s;
114*4882a593Smuzhiyun unsigned long max_d;
115*4882a593Smuzhiyun unsigned long maxa_s;
116*4882a593Smuzhiyun unsigned long maxa_d;
117*4882a593Smuzhiyun unsigned long min_s;
118*4882a593Smuzhiyun unsigned long min_d;
119*4882a593Smuzhiyun unsigned long mina_s;
120*4882a593Smuzhiyun unsigned long mina_d;
121*4882a593Smuzhiyun unsigned long mov_s;
122*4882a593Smuzhiyun unsigned long mov_d;
123*4882a593Smuzhiyun unsigned long msubf_s;
124*4882a593Smuzhiyun unsigned long msubf_d;
125*4882a593Smuzhiyun unsigned long mul_s;
126*4882a593Smuzhiyun unsigned long mul_d;
127*4882a593Smuzhiyun unsigned long neg_s;
128*4882a593Smuzhiyun unsigned long neg_d;
129*4882a593Smuzhiyun unsigned long recip_s;
130*4882a593Smuzhiyun unsigned long recip_d;
131*4882a593Smuzhiyun unsigned long rint_s;
132*4882a593Smuzhiyun unsigned long rint_d;
133*4882a593Smuzhiyun unsigned long round_w_s;
134*4882a593Smuzhiyun unsigned long round_w_d;
135*4882a593Smuzhiyun unsigned long round_l_s;
136*4882a593Smuzhiyun unsigned long round_l_d;
137*4882a593Smuzhiyun unsigned long rsqrt_s;
138*4882a593Smuzhiyun unsigned long rsqrt_d;
139*4882a593Smuzhiyun unsigned long sel_s;
140*4882a593Smuzhiyun unsigned long sel_d;
141*4882a593Smuzhiyun unsigned long seleqz_s;
142*4882a593Smuzhiyun unsigned long seleqz_d;
143*4882a593Smuzhiyun unsigned long selnez_s;
144*4882a593Smuzhiyun unsigned long selnez_d;
145*4882a593Smuzhiyun unsigned long sqrt_s;
146*4882a593Smuzhiyun unsigned long sqrt_d;
147*4882a593Smuzhiyun unsigned long sub_s;
148*4882a593Smuzhiyun unsigned long sub_d;
149*4882a593Smuzhiyun unsigned long trunc_w_s;
150*4882a593Smuzhiyun unsigned long trunc_w_d;
151*4882a593Smuzhiyun unsigned long trunc_l_s;
152*4882a593Smuzhiyun unsigned long trunc_l_d;
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun #define MIPS_FPU_EMU_INC_STATS(M) \
158*4882a593Smuzhiyun do { \
159*4882a593Smuzhiyun preempt_disable(); \
160*4882a593Smuzhiyun __this_cpu_inc(fpuemustats.M); \
161*4882a593Smuzhiyun preempt_enable(); \
162*4882a593Smuzhiyun } while (0)
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun #else
165*4882a593Smuzhiyun #define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
166*4882a593Smuzhiyun #endif /* CONFIG_DEBUG_FS */
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
169*4882a593Smuzhiyun struct mips_fpu_struct *ctx, int has_fpu,
170*4882a593Smuzhiyun void __user **fault_addr);
171*4882a593Smuzhiyun void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
172*4882a593Smuzhiyun struct task_struct *tsk);
173*4882a593Smuzhiyun int process_fpemu_return(int sig, void __user *fault_addr,
174*4882a593Smuzhiyun unsigned long fcr31);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /*
177*4882a593Smuzhiyun * Mask the FCSR Cause bits according to the Enable bits, observing
178*4882a593Smuzhiyun * that Unimplemented is always enabled.
179*4882a593Smuzhiyun */
mask_fcr31_x(unsigned long fcr31)180*4882a593Smuzhiyun static inline unsigned long mask_fcr31_x(unsigned long fcr31)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun return fcr31 & (FPU_CSR_UNI_X |
183*4882a593Smuzhiyun ((fcr31 & FPU_CSR_ALL_E) <<
184*4882a593Smuzhiyun (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E))));
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun #endif /* _ASM_FPU_EMULATOR_H */
188