1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef ASM_EDAC_H
3*4882a593Smuzhiyun #define ASM_EDAC_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <asm/compiler.h>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun /* ECC atomic, DMA, SMP and interrupt safe scrub function */
8*4882a593Smuzhiyun
edac_atomic_scrub(void * va,u32 size)9*4882a593Smuzhiyun static inline void edac_atomic_scrub(void *va, u32 size)
10*4882a593Smuzhiyun {
11*4882a593Smuzhiyun unsigned long *virt_addr = va;
12*4882a593Smuzhiyun unsigned long temp;
13*4882a593Smuzhiyun u32 i;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun for (i = 0; i < size / sizeof(unsigned long); i++) {
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * Very carefully read and write to memory atomically
18*4882a593Smuzhiyun * so we are interrupt, DMA and SMP safe.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Intel: asm("lock; addl $0, %0"::"m"(*virt_addr));
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun __asm__ __volatile__ (
24*4882a593Smuzhiyun " .set push \n"
25*4882a593Smuzhiyun " .set mips2 \n"
26*4882a593Smuzhiyun "1: ll %0, %1 # edac_atomic_scrub \n"
27*4882a593Smuzhiyun " addu %0, $0 \n"
28*4882a593Smuzhiyun " sc %0, %1 \n"
29*4882a593Smuzhiyun " beqz %0, 1b \n"
30*4882a593Smuzhiyun " .set pop \n"
31*4882a593Smuzhiyun : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*virt_addr)
32*4882a593Smuzhiyun : GCC_OFF_SMALL_ASM() (*virt_addr));
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun virt_addr++;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #endif
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