1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2005 Mips Technologies 4*4882a593Smuzhiyun * Author: Chris Dearman, chris@mips.com derived from fpu.h 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_DSP_H 7*4882a593Smuzhiyun #define _ASM_DSP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <asm/cpu.h> 10*4882a593Smuzhiyun #include <asm/cpu-features.h> 11*4882a593Smuzhiyun #include <asm/hazards.h> 12*4882a593Smuzhiyun #include <asm/mipsregs.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define DSP_DEFAULT 0x00000000 15*4882a593Smuzhiyun #define DSP_MASK 0x3f 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define __enable_dsp_hazard() \ 18*4882a593Smuzhiyun do { \ 19*4882a593Smuzhiyun asm("_ehb"); \ 20*4882a593Smuzhiyun } while (0) 21*4882a593Smuzhiyun __init_dsp(void)22*4882a593Smuzhiyunstatic inline void __init_dsp(void) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun mthi1(0); 25*4882a593Smuzhiyun mtlo1(0); 26*4882a593Smuzhiyun mthi2(0); 27*4882a593Smuzhiyun mtlo2(0); 28*4882a593Smuzhiyun mthi3(0); 29*4882a593Smuzhiyun mtlo3(0); 30*4882a593Smuzhiyun wrdsp(DSP_DEFAULT, DSP_MASK); 31*4882a593Smuzhiyun } 32*4882a593Smuzhiyun init_dsp(void)33*4882a593Smuzhiyunstatic inline void init_dsp(void) 34*4882a593Smuzhiyun { 35*4882a593Smuzhiyun if (cpu_has_dsp) 36*4882a593Smuzhiyun __init_dsp(); 37*4882a593Smuzhiyun } 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define __save_dsp(tsk) \ 40*4882a593Smuzhiyun do { \ 41*4882a593Smuzhiyun tsk->thread.dsp.dspr[0] = mfhi1(); \ 42*4882a593Smuzhiyun tsk->thread.dsp.dspr[1] = mflo1(); \ 43*4882a593Smuzhiyun tsk->thread.dsp.dspr[2] = mfhi2(); \ 44*4882a593Smuzhiyun tsk->thread.dsp.dspr[3] = mflo2(); \ 45*4882a593Smuzhiyun tsk->thread.dsp.dspr[4] = mfhi3(); \ 46*4882a593Smuzhiyun tsk->thread.dsp.dspr[5] = mflo3(); \ 47*4882a593Smuzhiyun tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); \ 48*4882a593Smuzhiyun } while (0) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define save_dsp(tsk) \ 51*4882a593Smuzhiyun do { \ 52*4882a593Smuzhiyun if (cpu_has_dsp) \ 53*4882a593Smuzhiyun __save_dsp(tsk); \ 54*4882a593Smuzhiyun } while (0) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define __restore_dsp(tsk) \ 57*4882a593Smuzhiyun do { \ 58*4882a593Smuzhiyun mthi1(tsk->thread.dsp.dspr[0]); \ 59*4882a593Smuzhiyun mtlo1(tsk->thread.dsp.dspr[1]); \ 60*4882a593Smuzhiyun mthi2(tsk->thread.dsp.dspr[2]); \ 61*4882a593Smuzhiyun mtlo2(tsk->thread.dsp.dspr[3]); \ 62*4882a593Smuzhiyun mthi3(tsk->thread.dsp.dspr[4]); \ 63*4882a593Smuzhiyun mtlo3(tsk->thread.dsp.dspr[5]); \ 64*4882a593Smuzhiyun wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK); \ 65*4882a593Smuzhiyun } while (0) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define restore_dsp(tsk) \ 68*4882a593Smuzhiyun do { \ 69*4882a593Smuzhiyun if (cpu_has_dsp) \ 70*4882a593Smuzhiyun __restore_dsp(tsk); \ 71*4882a593Smuzhiyun } while (0) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define __get_dsp_regs(tsk) \ 74*4882a593Smuzhiyun ({ \ 75*4882a593Smuzhiyun if (tsk == current) \ 76*4882a593Smuzhiyun __save_dsp(current); \ 77*4882a593Smuzhiyun \ 78*4882a593Smuzhiyun tsk->thread.dsp.dspr; \ 79*4882a593Smuzhiyun }) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* _ASM_DSP_H */ 82