1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/asm-mips/dec/kn05.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min 6*4882a593Smuzhiyun * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or 7*4882a593Smuzhiyun * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC 8*4882a593Smuzhiyun * definitions. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * WARNING! All this information is pure guesswork based on the 13*4882a593Smuzhiyun * ROM. It is provided here in hope it will give someone some 14*4882a593Smuzhiyun * food for thought. No documentation for the KN05 nor the KN04 15*4882a593Smuzhiyun * module has been located so far. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #ifndef __ASM_MIPS_DEC_KN05_H 18*4882a593Smuzhiyun #define __ASM_MIPS_DEC_KN05_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <asm/dec/ioasic_addrs.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * The oncard MB (Memory Buffer) ASIC provides an additional address 24*4882a593Smuzhiyun * decoder. Certain address ranges within the "high" 16 slots are 25*4882a593Smuzhiyun * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA. 26*4882a593Smuzhiyun * Others are handled locally. "Low" slots are always passed. 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define KN4K_SLOT_BASE 0x1fc00000 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */ 31*4882a593Smuzhiyun #define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */ 32*4882a593Smuzhiyun #define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */ 33*4882a593Smuzhiyun #define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */ 34*4882a593Smuzhiyun #define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */ 35*4882a593Smuzhiyun #define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */ 36*4882a593Smuzhiyun #define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */ 37*4882a593Smuzhiyun #define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */ 38*4882a593Smuzhiyun #define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */ 39*4882a593Smuzhiyun #define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */ 40*4882a593Smuzhiyun #define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */ 41*4882a593Smuzhiyun #define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */ 42*4882a593Smuzhiyun #define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ 43*4882a593Smuzhiyun #define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */ 44*4882a593Smuzhiyun #define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */ 45*4882a593Smuzhiyun #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * MB ASIC interrupt bits. 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define KN4K_MB_INR_MB 4 /* ??? */ 51*4882a593Smuzhiyun #define KN4K_MB_INR_MT 3 /* memory, I/O bus read/write errors */ 52*4882a593Smuzhiyun #define KN4K_MB_INR_RES_2 2 /* unused */ 53*4882a593Smuzhiyun #define KN4K_MB_INR_RTC 1 /* RTC */ 54*4882a593Smuzhiyun #define KN4K_MB_INR_TC 0 /* I/O ASIC cascade */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * Bits for the MB interrupt register. 58*4882a593Smuzhiyun * The register appears read-only. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define KN4K_MB_INT_IRQ (0x1f<<0) /* CPU Int[4:0] status. */ 61*4882a593Smuzhiyun #define KN4K_MB_INT_IRQ_N(n) (1<<(n)) /* Individual status bits. */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * Bits for the MB control & status register. 65*4882a593Smuzhiyun * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware. 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun #define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ 68*4882a593Smuzhiyun #define KN4K_MB_CSR_F (1<<1) /* ??? */ 69*4882a593Smuzhiyun #define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */ 70*4882a593Smuzhiyun #define KN4K_MB_CSR_OD (1<<10) /* ??? */ 71*4882a593Smuzhiyun #define KN4K_MB_CSR_CP (1<<11) /* ??? */ 72*4882a593Smuzhiyun #define KN4K_MB_CSR_UNC (1<<12) /* ??? */ 73*4882a593Smuzhiyun #define KN4K_MB_CSR_IM (1<<13) /* ??? */ 74*4882a593Smuzhiyun #define KN4K_MB_CSR_NC (1<<14) /* ??? */ 75*4882a593Smuzhiyun #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ 76*4882a593Smuzhiyun #define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ 77*4882a593Smuzhiyun #define KN4K_MB_CSR_MSK_N(n) (1<<((n)+16)) /* Individual mask bits. */ 78*4882a593Smuzhiyun #define KN4K_MB_CSR_FW (1<<21) /* ??? */ 79*4882a593Smuzhiyun #define KN4K_MB_CSR_W (1<<31) /* ??? */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* __ASM_MIPS_DEC_KN05_H */ 82