1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/asm-mips/dec/kn02ba.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * DECstation 5000/1xx (3min or KN02-BA) definitions. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2002, 2003 Maciej W. Rozycki 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ASM_MIPS_DEC_KN02BA_H 10*4882a593Smuzhiyun #define __ASM_MIPS_DEC_KN02BA_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/dec/kn02xa.h> /* For common definitions. */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * CPU interrupt bits. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define KN02BA_CPU_INR_HALT 6 /* HALT button */ 18*4882a593Smuzhiyun #define KN02BA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */ 19*4882a593Smuzhiyun #define KN02BA_CPU_INR_TC2 4 /* TURBOchannel slot #2 */ 20*4882a593Smuzhiyun #define KN02BA_CPU_INR_TC1 3 /* TURBOchannel slot #1 */ 21*4882a593Smuzhiyun #define KN02BA_CPU_INR_TC0 2 /* TURBOchannel slot #0 */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * I/O ASIC interrupt bits. Star marks denote non-IRQ status bits. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define KN02BA_IO_INR_RES_15 15 /* unused */ 27*4882a593Smuzhiyun #define KN02BA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */ 28*4882a593Smuzhiyun #define KN02BA_IO_INR_RES_13 13 /* unused */ 29*4882a593Smuzhiyun #define KN02BA_IO_INR_BUS 12 /* memory, I/O bus read/write errors */ 30*4882a593Smuzhiyun #define KN02BA_IO_INR_RES_11 11 /* unused */ 31*4882a593Smuzhiyun #define KN02BA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */ 32*4882a593Smuzhiyun #define KN02BA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */ 33*4882a593Smuzhiyun #define KN02BA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */ 34*4882a593Smuzhiyun #define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */ 35*4882a593Smuzhiyun #define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */ 36*4882a593Smuzhiyun #define KN02BA_IO_INR_RTC 5 /* DS1287 RTC */ 37*4882a593Smuzhiyun #define KN02BA_IO_INR_PSU 4 /* power supply unit warning */ 38*4882a593Smuzhiyun #define KN02BA_IO_INR_RES_3 3 /* unused */ 39*4882a593Smuzhiyun #define KN02BA_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */ 40*4882a593Smuzhiyun #define KN02BA_IO_INR_PBNC 1 /* ~HALT button debouncer */ 41*4882a593Smuzhiyun #define KN02BA_IO_INR_PBNO 0 /* HALT button debouncer */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * Memory Error Register bits. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define KN02BA_MER_RES_27 (1<<27) /* unused */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Memory Size Register bits. 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define KN02BA_MSR_RES_17 (0x3ff<<17) /* unused */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * I/O ASIC System Support Register bits. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define KN02BA_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */ 58*4882a593Smuzhiyun #define KN02BA_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */ 59*4882a593Smuzhiyun #define KN02BA_IO_SSR_RES_12 (1<<12) /* unused */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define KN02BA_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* __ASM_MIPS_DEC_KN02BA_H */ 64