1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Miscellaneous definitions used to initialise the interrupt vector table 3*4882a593Smuzhiyun * with the machine-specific interrupt routines. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 6*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 7*4882a593Smuzhiyun * for more details. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Copyright (C) 1997 by Paul M. Antoine. 10*4882a593Smuzhiyun * reworked 1998 by Harald Koerfgen. 11*4882a593Smuzhiyun * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASM_DEC_INTERRUPTS_H 15*4882a593Smuzhiyun #define __ASM_DEC_INTERRUPTS_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <irq.h> 18*4882a593Smuzhiyun #include <asm/mipsregs.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * The list of possible system devices which provide an 23*4882a593Smuzhiyun * interrupt. Not all devices exist on a given system. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Ordinary interrupts */ 28*4882a593Smuzhiyun #define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */ 29*4882a593Smuzhiyun #define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */ 30*4882a593Smuzhiyun #define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */ 31*4882a593Smuzhiyun #define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */ 32*4882a593Smuzhiyun #define DEC_IRQ_FLOPPY 5 /* 82077 FDC */ 33*4882a593Smuzhiyun #define DEC_IRQ_FPU 6 /* R3k FPU */ 34*4882a593Smuzhiyun #define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */ 35*4882a593Smuzhiyun #define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */ 36*4882a593Smuzhiyun #define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */ 37*4882a593Smuzhiyun #define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */ 38*4882a593Smuzhiyun #define DEC_IRQ_PSU 11 /* power supply unit warning */ 39*4882a593Smuzhiyun #define DEC_IRQ_RTC 12 /* DS1287 RTC */ 40*4882a593Smuzhiyun #define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */ 41*4882a593Smuzhiyun #define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */ 42*4882a593Smuzhiyun #define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */ 43*4882a593Smuzhiyun #define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */ 44*4882a593Smuzhiyun #define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */ 45*4882a593Smuzhiyun #define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */ 46*4882a593Smuzhiyun #define DEC_IRQ_TIMER 19 /* ARC periodic timer */ 47*4882a593Smuzhiyun #define DEC_IRQ_VIDEO 20 /* framebuffer */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* I/O ASIC DMA interrupts */ 50*4882a593Smuzhiyun #define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */ 51*4882a593Smuzhiyun #define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */ 52*4882a593Smuzhiyun #define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */ 53*4882a593Smuzhiyun #define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */ 54*4882a593Smuzhiyun #define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */ 55*4882a593Smuzhiyun #define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */ 56*4882a593Smuzhiyun #define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */ 57*4882a593Smuzhiyun #define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */ 58*4882a593Smuzhiyun #define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */ 59*4882a593Smuzhiyun #define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */ 60*4882a593Smuzhiyun #define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */ 61*4882a593Smuzhiyun #define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */ 62*4882a593Smuzhiyun #define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */ 63*4882a593Smuzhiyun #define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */ 64*4882a593Smuzhiyun #define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */ 65*4882a593Smuzhiyun #define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */ 66*4882a593Smuzhiyun #define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */ 67*4882a593Smuzhiyun #define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */ 68*4882a593Smuzhiyun #define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */ 69*4882a593Smuzhiyun #define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* TC5 & TC6 are virtual slots for KN02's onboard devices */ 72*4882a593Smuzhiyun #define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */ 73*4882a593Smuzhiyun #define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define DEC_NR_INTS 41 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Largest of cpu mask_nr tables. */ 79*4882a593Smuzhiyun #define DEC_MAX_CPU_INTS 6 80*4882a593Smuzhiyun /* Largest of asic mask_nr tables. */ 81*4882a593Smuzhiyun #define DEC_MAX_ASIC_INTS 9 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * CPU interrupt bits common to all systems. 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun #define DEC_CPU_INR_FPU 7 /* R3k FPU */ 88*4882a593Smuzhiyun #define DEC_CPU_INR_SW1 1 /* software #1 */ 89*4882a593Smuzhiyun #define DEC_CPU_INR_SW0 0 /* software #0 */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) 94*4882a593Smuzhiyun #define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP)) 95*4882a593Smuzhiyun #define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * Interrupt table structures to hide differences between systems. 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun typedef union { int i; void *p; } int_ptr; 104*4882a593Smuzhiyun extern int dec_interrupt[DEC_NR_INTS]; 105*4882a593Smuzhiyun extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2]; 106*4882a593Smuzhiyun extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2]; 107*4882a593Smuzhiyun extern int cpu_fpu_mask; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * Common interrupt routine prototypes for all DECStations 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun extern void kn02_io_int(void); 114*4882a593Smuzhiyun extern void kn02xa_io_int(void); 115*4882a593Smuzhiyun extern void kn03_io_int(void); 116*4882a593Smuzhiyun extern void asic_dma_int(void); 117*4882a593Smuzhiyun extern void asic_all_int(void); 118*4882a593Smuzhiyun extern void kn02_all_int(void); 119*4882a593Smuzhiyun extern void cpu_all_int(void); 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun extern void dec_intr_unimplemented(void); 122*4882a593Smuzhiyun extern void asic_intr_unimplemented(void); 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #endif 127