1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/asm-mips/dec/ecc.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * ECC handling logic definitions common to DECstation/DECsystem 6*4882a593Smuzhiyun * 5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and 7*4882a593Smuzhiyun * DECsystem 5900 (KN03), 5900/260 (KN05) systems. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Copyright (C) 2003 Maciej W. Rozycki 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __ASM_MIPS_DEC_ECC_H 12*4882a593Smuzhiyun #define __ASM_MIPS_DEC_ECC_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Error Address Register bits. 16*4882a593Smuzhiyun * The register is r/wc -- any write clears it. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define KN0X_EAR_VALID (1<<31) /* error data valid, bus IRQ */ 19*4882a593Smuzhiyun #define KN0X_EAR_CPU (1<<30) /* CPU/DMA transaction */ 20*4882a593Smuzhiyun #define KN0X_EAR_WRITE (1<<29) /* write/read transaction */ 21*4882a593Smuzhiyun #define KN0X_EAR_ECCERR (1<<28) /* ECC/timeout or overrun */ 22*4882a593Smuzhiyun #define KN0X_EAR_RES_27 (1<<27) /* unused */ 23*4882a593Smuzhiyun #define KN0X_EAR_ADDRESS (0x7ffffff<<0) /* address involved */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Error Syndrome Register bits. 27*4882a593Smuzhiyun * The register is frozen when EAR.VALID is set, otherwise it records bits 28*4882a593Smuzhiyun * from the last memory read. The register is r/wc -- any write clears it. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define KN0X_ESR_VLDHI (1<<31) /* error data valid hi word */ 31*4882a593Smuzhiyun #define KN0X_ESR_CHKHI (0x7f<<24) /* check bits read from mem */ 32*4882a593Smuzhiyun #define KN0X_ESR_SNGHI (1<<23) /* single/double bit error */ 33*4882a593Smuzhiyun #define KN0X_ESR_SYNHI (0x7f<<16) /* syndrome from ECC logic */ 34*4882a593Smuzhiyun #define KN0X_ESR_VLDLO (1<<15) /* error data valid lo word */ 35*4882a593Smuzhiyun #define KN0X_ESR_CHKLO (0x7f<<8) /* check bits read from mem */ 36*4882a593Smuzhiyun #define KN0X_ESR_SNGLO (1<<7) /* single/double bit error */ 37*4882a593Smuzhiyun #define KN0X_ESR_SYNLO (0x7f<<0) /* syndrome from ECC logic */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #include <linux/interrupt.h> 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct pt_regs; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun extern void dec_ecc_be_init(void); 47*4882a593Smuzhiyun extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup); 48*4882a593Smuzhiyun extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id); 49*4882a593Smuzhiyun #endif 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* __ASM_MIPS_DEC_ECC_H */ 52