1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Cache operations for the cache instruction. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 5*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 6*4882a593Smuzhiyun * for more details. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle 9*4882a593Smuzhiyun * (C) Copyright 1999 Silicon Graphics, Inc. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __ASM_CACHEOPS_H 12*4882a593Smuzhiyun #define __ASM_CACHEOPS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Most cache ops are split into a 2 bit field identifying the cache, and a 3 16*4882a593Smuzhiyun * bit field identifying the cache operation. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define CacheOp_Cache 0x03 19*4882a593Smuzhiyun #define CacheOp_Op 0x1c 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define Cache_I 0x00 22*4882a593Smuzhiyun #define Cache_D 0x01 23*4882a593Smuzhiyun #define Cache_T 0x02 24*4882a593Smuzhiyun #define Cache_V 0x02 /* Loongson-3 */ 25*4882a593Smuzhiyun #define Cache_S 0x03 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define Index_Writeback_Inv 0x00 28*4882a593Smuzhiyun #define Index_Load_Tag 0x04 29*4882a593Smuzhiyun #define Index_Store_Tag 0x08 30*4882a593Smuzhiyun #define Hit_Invalidate 0x10 31*4882a593Smuzhiyun #define Hit_Writeback_Inv 0x14 /* not with Cache_I though */ 32*4882a593Smuzhiyun #define Hit_Writeback 0x18 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * Cache Operations available on all MIPS processors with R4000-style caches 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define Index_Invalidate_I (Cache_I | Index_Writeback_Inv) 38*4882a593Smuzhiyun #define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv) 39*4882a593Smuzhiyun #define Index_Load_Tag_I (Cache_I | Index_Load_Tag) 40*4882a593Smuzhiyun #define Index_Load_Tag_D (Cache_D | Index_Load_Tag) 41*4882a593Smuzhiyun #define Index_Store_Tag_I (Cache_I | Index_Store_Tag) 42*4882a593Smuzhiyun #define Index_Store_Tag_D (Cache_D | Index_Store_Tag) 43*4882a593Smuzhiyun #define Hit_Invalidate_I (Cache_I | Hit_Invalidate) 44*4882a593Smuzhiyun #define Hit_Invalidate_D (Cache_D | Hit_Invalidate) 45*4882a593Smuzhiyun #define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * R4000-specific cacheops 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define Create_Dirty_Excl_D (Cache_D | 0x0c) 51*4882a593Smuzhiyun #define Fill_I (Cache_I | 0x14) 52*4882a593Smuzhiyun #define Hit_Writeback_I (Cache_I | Hit_Writeback) 53*4882a593Smuzhiyun #define Hit_Writeback_D (Cache_D | Hit_Writeback) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * R4000SC and R4400SC-specific cacheops 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define Cache_SI 0x02 59*4882a593Smuzhiyun #define Cache_SD 0x03 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define Index_Invalidate_SI (Cache_SI | Index_Writeback_Inv) 62*4882a593Smuzhiyun #define Index_Writeback_Inv_SD (Cache_SD | Index_Writeback_Inv) 63*4882a593Smuzhiyun #define Index_Load_Tag_SI (Cache_SI | Index_Load_Tag) 64*4882a593Smuzhiyun #define Index_Load_Tag_SD (Cache_SD | Index_Load_Tag) 65*4882a593Smuzhiyun #define Index_Store_Tag_SI (Cache_SI | Index_Store_Tag) 66*4882a593Smuzhiyun #define Index_Store_Tag_SD (Cache_SD | Index_Store_Tag) 67*4882a593Smuzhiyun #define Create_Dirty_Excl_SD (Cache_SD | 0x0c) 68*4882a593Smuzhiyun #define Hit_Invalidate_SI (Cache_SI | Hit_Invalidate) 69*4882a593Smuzhiyun #define Hit_Invalidate_SD (Cache_SD | Hit_Invalidate) 70*4882a593Smuzhiyun #define Hit_Writeback_Inv_SD (Cache_SD | Hit_Writeback_Inv) 71*4882a593Smuzhiyun #define Hit_Writeback_SD (Cache_SD | Hit_Writeback) 72*4882a593Smuzhiyun #define Hit_Set_Virtual_SI (Cache_SI | 0x1c) 73*4882a593Smuzhiyun #define Hit_Set_Virtual_SD (Cache_SD | 0x1c) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * R5000-specific cacheops 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #define R5K_Page_Invalidate_S (Cache_S | 0x14) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * RM7000-specific cacheops 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun #define Page_Invalidate_T (Cache_T | 0x14) 84*4882a593Smuzhiyun #define Index_Store_Tag_T (Cache_T | Index_Store_Tag) 85*4882a593Smuzhiyun #define Index_Load_Tag_T (Cache_T | Index_Load_Tag) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * R10000-specific cacheops 89*4882a593Smuzhiyun * 90*4882a593Smuzhiyun * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 91*4882a593Smuzhiyun * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun #define Index_Writeback_Inv_S (Cache_S | Index_Writeback_Inv) 94*4882a593Smuzhiyun #define Index_Load_Tag_S (Cache_S | Index_Load_Tag) 95*4882a593Smuzhiyun #define Index_Store_Tag_S (Cache_S | Index_Store_Tag) 96*4882a593Smuzhiyun #define Hit_Invalidate_S (Cache_S | Hit_Invalidate) 97*4882a593Smuzhiyun #define Cache_Barrier 0x14 98*4882a593Smuzhiyun #define Hit_Writeback_Inv_S (Cache_S | Hit_Writeback_Inv) 99*4882a593Smuzhiyun #define Index_Load_Data_I (Cache_I | 0x18) 100*4882a593Smuzhiyun #define Index_Load_Data_D (Cache_D | 0x18) 101*4882a593Smuzhiyun #define Index_Load_Data_S (Cache_S | 0x18) 102*4882a593Smuzhiyun #define Index_Store_Data_I (Cache_I | 0x1c) 103*4882a593Smuzhiyun #define Index_Store_Data_D (Cache_D | 0x1c) 104*4882a593Smuzhiyun #define Index_Store_Data_S (Cache_S | 0x1c) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * Loongson2-specific cacheops 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun #define Hit_Invalidate_I_Loongson2 (Cache_I | 0x00) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* 112*4882a593Smuzhiyun * Loongson3-specific cacheops 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun #define Index_Writeback_Inv_V (Cache_V | Index_Writeback_Inv) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif /* __ASM_CACHEOPS_H */ 117