1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun * for more details.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #ifndef _ASM_BRANCH_H
9*4882a593Smuzhiyun #define _ASM_BRANCH_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/cpu-features.h>
12*4882a593Smuzhiyun #include <asm/mipsregs.h>
13*4882a593Smuzhiyun #include <asm/ptrace.h>
14*4882a593Smuzhiyun #include <asm/inst.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun extern int __isa_exception_epc(struct pt_regs *regs);
17*4882a593Smuzhiyun extern int __compute_return_epc(struct pt_regs *regs);
18*4882a593Smuzhiyun extern int __compute_return_epc_for_insn(struct pt_regs *regs,
19*4882a593Smuzhiyun union mips_instruction insn);
20*4882a593Smuzhiyun extern int __microMIPS_compute_return_epc(struct pt_regs *regs);
21*4882a593Smuzhiyun extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * microMIPS bitfields
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun #define MM_POOL32A_MINOR_MASK 0x3f
27*4882a593Smuzhiyun #define MM_POOL32A_MINOR_SHIFT 0x6
28*4882a593Smuzhiyun #define MM_MIPS32_COND_FC 0x30
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun int isBranchInstr(struct pt_regs *regs,
31*4882a593Smuzhiyun struct mm_decoded_insn dec_insn, unsigned long *contpc);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun extern int __mm_isBranchInstr(struct pt_regs *regs,
34*4882a593Smuzhiyun struct mm_decoded_insn dec_insn, unsigned long *contpc);
35*4882a593Smuzhiyun
mm_isBranchInstr(struct pt_regs * regs,struct mm_decoded_insn dec_insn,unsigned long * contpc)36*4882a593Smuzhiyun static inline int mm_isBranchInstr(struct pt_regs *regs,
37*4882a593Smuzhiyun struct mm_decoded_insn dec_insn, unsigned long *contpc)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun if (!cpu_has_mmips)
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return __mm_isBranchInstr(regs, dec_insn, contpc);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
delay_slot(struct pt_regs * regs)45*4882a593Smuzhiyun static inline int delay_slot(struct pt_regs *regs)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun return regs->cp0_cause & CAUSEF_BD;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
clear_delay_slot(struct pt_regs * regs)50*4882a593Smuzhiyun static inline void clear_delay_slot(struct pt_regs *regs)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun regs->cp0_cause &= ~CAUSEF_BD;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
set_delay_slot(struct pt_regs * regs)55*4882a593Smuzhiyun static inline void set_delay_slot(struct pt_regs *regs)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun regs->cp0_cause |= CAUSEF_BD;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
exception_epc(struct pt_regs * regs)60*4882a593Smuzhiyun static inline unsigned long exception_epc(struct pt_regs *regs)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun if (likely(!delay_slot(regs)))
63*4882a593Smuzhiyun return regs->cp0_epc;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (get_isa16_mode(regs->cp0_epc))
66*4882a593Smuzhiyun return __isa_exception_epc(regs);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return regs->cp0_epc + 4;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define BRANCH_LIKELY_TAKEN 0x0001
72*4882a593Smuzhiyun
compute_return_epc(struct pt_regs * regs)73*4882a593Smuzhiyun static inline int compute_return_epc(struct pt_regs *regs)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun if (get_isa16_mode(regs->cp0_epc)) {
76*4882a593Smuzhiyun if (cpu_has_mmips)
77*4882a593Smuzhiyun return __microMIPS_compute_return_epc(regs);
78*4882a593Smuzhiyun if (cpu_has_mips16)
79*4882a593Smuzhiyun return __MIPS16e_compute_return_epc(regs);
80*4882a593Smuzhiyun } else if (!delay_slot(regs)) {
81*4882a593Smuzhiyun regs->cp0_epc += 4;
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return __compute_return_epc(regs);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
MIPS16e_compute_return_epc(struct pt_regs * regs,union mips16e_instruction * inst)88*4882a593Smuzhiyun static inline int MIPS16e_compute_return_epc(struct pt_regs *regs,
89*4882a593Smuzhiyun union mips16e_instruction *inst)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun if (likely(!delay_slot(regs))) {
92*4882a593Smuzhiyun if (inst->ri.opcode == MIPS16e_extend_op) {
93*4882a593Smuzhiyun regs->cp0_epc += 4;
94*4882a593Smuzhiyun return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun regs->cp0_epc += 2;
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return __MIPS16e_compute_return_epc(regs);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #endif /* _ASM_BRANCH_H */
104