1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Definitions for BMIPS processors 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef _ASM_BMIPS_H 11*4882a593Smuzhiyun #define _ASM_BMIPS_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/compiler.h> 14*4882a593Smuzhiyun #include <linux/linkage.h> 15*4882a593Smuzhiyun #include <asm/addrspace.h> 16*4882a593Smuzhiyun #include <asm/mipsregs.h> 17*4882a593Smuzhiyun #include <asm/hazards.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */ 20*4882a593Smuzhiyun #define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \ 21*4882a593Smuzhiyun (unsigned long) \ 22*4882a593Smuzhiyun ((read_c0_brcm_cbr() >> 18) << 18))) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define BMIPS_RAC_CONFIG 0x00000000 25*4882a593Smuzhiyun #define BMIPS_RAC_ADDRESS_RANGE 0x00000004 26*4882a593Smuzhiyun #define BMIPS_RAC_CONFIG_1 0x00000008 27*4882a593Smuzhiyun #define BMIPS_L2_CONFIG 0x0000000c 28*4882a593Smuzhiyun #define BMIPS_LMB_CONTROL 0x0000001c 29*4882a593Smuzhiyun #define BMIPS_SYSTEM_BASE 0x00000020 30*4882a593Smuzhiyun #define BMIPS_PERF_GLOBAL_CONTROL 0x00020000 31*4882a593Smuzhiyun #define BMIPS_PERF_CONTROL_0 0x00020004 32*4882a593Smuzhiyun #define BMIPS_PERF_CONTROL_1 0x00020008 33*4882a593Smuzhiyun #define BMIPS_PERF_COUNTER_0 0x00020010 34*4882a593Smuzhiyun #define BMIPS_PERF_COUNTER_1 0x00020014 35*4882a593Smuzhiyun #define BMIPS_PERF_COUNTER_2 0x00020018 36*4882a593Smuzhiyun #define BMIPS_PERF_COUNTER_3 0x0002001c 37*4882a593Smuzhiyun #define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000 38*4882a593Smuzhiyun #define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define BMIPS_NMI_RESET_VEC 0x80000000 41*4882a593Smuzhiyun #define BMIPS_WARM_RESTART_VEC 0x80000380 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define ZSCM_REG_BASE 0x97000000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #if !defined(__ASSEMBLY__) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #include <linux/cpumask.h> 48*4882a593Smuzhiyun #include <asm/r4kcache.h> 49*4882a593Smuzhiyun #include <asm/smp-ops.h> 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun extern const struct plat_smp_ops bmips43xx_smp_ops; 52*4882a593Smuzhiyun extern const struct plat_smp_ops bmips5000_smp_ops; 53*4882a593Smuzhiyun register_bmips_smp_ops(void)54*4882a593Smuzhiyunstatic inline int register_bmips_smp_ops(void) 55*4882a593Smuzhiyun { 56*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP) 57*4882a593Smuzhiyun switch (current_cpu_type()) { 58*4882a593Smuzhiyun case CPU_BMIPS32: 59*4882a593Smuzhiyun case CPU_BMIPS3300: 60*4882a593Smuzhiyun return register_up_smp_ops(); 61*4882a593Smuzhiyun case CPU_BMIPS4350: 62*4882a593Smuzhiyun case CPU_BMIPS4380: 63*4882a593Smuzhiyun register_smp_ops(&bmips43xx_smp_ops); 64*4882a593Smuzhiyun break; 65*4882a593Smuzhiyun case CPU_BMIPS5000: 66*4882a593Smuzhiyun register_smp_ops(&bmips5000_smp_ops); 67*4882a593Smuzhiyun break; 68*4882a593Smuzhiyun default: 69*4882a593Smuzhiyun return -ENODEV; 70*4882a593Smuzhiyun } 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun return 0; 73*4882a593Smuzhiyun #else 74*4882a593Smuzhiyun return -ENODEV; 75*4882a593Smuzhiyun #endif 76*4882a593Smuzhiyun } 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun extern char bmips_reset_nmi_vec[]; 79*4882a593Smuzhiyun extern char bmips_reset_nmi_vec_end[]; 80*4882a593Smuzhiyun extern char bmips_smp_movevec[]; 81*4882a593Smuzhiyun extern char bmips_smp_int_vec[]; 82*4882a593Smuzhiyun extern char bmips_smp_int_vec_end[]; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun extern int bmips_smp_enabled; 85*4882a593Smuzhiyun extern int bmips_cpu_offset; 86*4882a593Smuzhiyun extern cpumask_t bmips_booted_mask; 87*4882a593Smuzhiyun extern unsigned long bmips_tp1_irqs; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun extern void bmips_ebase_setup(void); 90*4882a593Smuzhiyun extern asmlinkage void plat_wired_tlb_setup(void); 91*4882a593Smuzhiyun extern void bmips_cpu_setup(void); 92*4882a593Smuzhiyun bmips_read_zscm_reg(unsigned int offset)93*4882a593Smuzhiyunstatic inline unsigned long bmips_read_zscm_reg(unsigned int offset) 94*4882a593Smuzhiyun { 95*4882a593Smuzhiyun unsigned long ret; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun barrier(); 98*4882a593Smuzhiyun cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset); 99*4882a593Smuzhiyun __sync(); 100*4882a593Smuzhiyun _ssnop(); 101*4882a593Smuzhiyun _ssnop(); 102*4882a593Smuzhiyun _ssnop(); 103*4882a593Smuzhiyun _ssnop(); 104*4882a593Smuzhiyun _ssnop(); 105*4882a593Smuzhiyun _ssnop(); 106*4882a593Smuzhiyun _ssnop(); 107*4882a593Smuzhiyun ret = read_c0_ddatalo(); 108*4882a593Smuzhiyun _ssnop(); 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun return ret; 111*4882a593Smuzhiyun } 112*4882a593Smuzhiyun bmips_write_zscm_reg(unsigned int offset,unsigned long data)113*4882a593Smuzhiyunstatic inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data) 114*4882a593Smuzhiyun { 115*4882a593Smuzhiyun write_c0_ddatalo(data); 116*4882a593Smuzhiyun _ssnop(); 117*4882a593Smuzhiyun _ssnop(); 118*4882a593Smuzhiyun _ssnop(); 119*4882a593Smuzhiyun cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset); 120*4882a593Smuzhiyun _ssnop(); 121*4882a593Smuzhiyun _ssnop(); 122*4882a593Smuzhiyun _ssnop(); 123*4882a593Smuzhiyun barrier(); 124*4882a593Smuzhiyun } 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #endif /* !defined(__ASSEMBLY__) */ 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #endif /* _ASM_BMIPS_H */ 129