1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Support code for virtual Ranchu board for MIPS.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Miodrag Dinic <miodrag.dinic@mips.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/of_address.h>
9*4882a593Smuzhiyun #include <linux/types.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <asm/machine.h>
12*4882a593Smuzhiyun #include <asm/mipsregs.h>
13*4882a593Smuzhiyun #include <asm/time.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define GOLDFISH_TIMER_LOW 0x00
16*4882a593Smuzhiyun #define GOLDFISH_TIMER_HIGH 0x04
17*4882a593Smuzhiyun
read_rtc_time(void __iomem * base)18*4882a593Smuzhiyun static __init u64 read_rtc_time(void __iomem *base)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun u32 time_low;
21*4882a593Smuzhiyun u32 time_high;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * Reading the low address latches the high value
25*4882a593Smuzhiyun * as well so there is no fear that we may read
26*4882a593Smuzhiyun * inaccurate high value.
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun time_low = readl(base + GOLDFISH_TIMER_LOW);
29*4882a593Smuzhiyun time_high = readl(base + GOLDFISH_TIMER_HIGH);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun return ((u64)time_high << 32) | time_low;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
ranchu_measure_hpt_freq(void)34*4882a593Smuzhiyun static __init unsigned int ranchu_measure_hpt_freq(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun u64 rtc_start, rtc_current, rtc_delta;
37*4882a593Smuzhiyun unsigned int start, count;
38*4882a593Smuzhiyun struct device_node *np;
39*4882a593Smuzhiyun void __iomem *rtc_base;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "google,goldfish-rtc");
42*4882a593Smuzhiyun if (!np)
43*4882a593Smuzhiyun panic("%s(): Failed to find 'google,goldfish-rtc' dt node!",
44*4882a593Smuzhiyun __func__);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun rtc_base = of_iomap(np, 0);
47*4882a593Smuzhiyun if (!rtc_base)
48*4882a593Smuzhiyun panic("%s(): Failed to ioremap Goldfish RTC base!", __func__);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * Poll the nanosecond resolution RTC for one
52*4882a593Smuzhiyun * second to calibrate the CPU frequency.
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun rtc_start = read_rtc_time(rtc_base);
55*4882a593Smuzhiyun start = read_c0_count();
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun do {
58*4882a593Smuzhiyun rtc_current = read_rtc_time(rtc_base);
59*4882a593Smuzhiyun rtc_delta = rtc_current - rtc_start;
60*4882a593Smuzhiyun } while (rtc_delta < NSEC_PER_SEC);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun count = read_c0_count() - start;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * Make sure the frequency will be a round number.
66*4882a593Smuzhiyun * Without this correction, the returned value may vary
67*4882a593Smuzhiyun * between subsequent emulation executions.
68*4882a593Smuzhiyun *
69*4882a593Smuzhiyun * TODO: Set this value using device tree.
70*4882a593Smuzhiyun */
71*4882a593Smuzhiyun count += 5000;
72*4882a593Smuzhiyun count -= count % 10000;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun iounmap(rtc_base);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return count;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const struct of_device_id ranchu_of_match[] __initconst = {
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun .compatible = "mti,ranchu",
82*4882a593Smuzhiyun },
83*4882a593Smuzhiyun {}
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun MIPS_MACHINE(ranchu) = {
87*4882a593Smuzhiyun .matches = ranchu_of_match,
88*4882a593Smuzhiyun .measure_hpt_freq = ranchu_measure_hpt_freq,
89*4882a593Smuzhiyun };
90