1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Microsemi MIPS SoC support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2017 Microsemi Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <asm/machine.h>
8*4882a593Smuzhiyun #include <asm/prom.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define DEVCPU_GCB_CHIP_REGS_CHIP_ID 0x71070000
11*4882a593Smuzhiyun #define CHIP_ID_PART_ID GENMASK(27, 12)
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define OCELOT_PART_ID (0x7514 << 12)
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define UART_UART 0x70100000
16*4882a593Smuzhiyun
ocelot_detect(void)17*4882a593Smuzhiyun static __init bool ocelot_detect(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun u32 rev;
20*4882a593Smuzhiyun int idx;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Look for the TLB entry set up by redboot before trying to use it */
23*4882a593Smuzhiyun write_c0_entryhi(DEVCPU_GCB_CHIP_REGS_CHIP_ID);
24*4882a593Smuzhiyun mtc0_tlbw_hazard();
25*4882a593Smuzhiyun tlb_probe();
26*4882a593Smuzhiyun tlb_probe_hazard();
27*4882a593Smuzhiyun idx = read_c0_index();
28*4882a593Smuzhiyun if (idx < 0)
29*4882a593Smuzhiyun return 0;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* A TLB entry exists, lets assume its usable and check the CHIP ID */
32*4882a593Smuzhiyun rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun if ((rev & CHIP_ID_PART_ID) != OCELOT_PART_ID)
35*4882a593Smuzhiyun return 0;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Copy command line from bootloader early for Initrd detection */
38*4882a593Smuzhiyun if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) {
39*4882a593Smuzhiyun unsigned int prom_argc = fw_arg0;
40*4882a593Smuzhiyun const char **prom_argv = (const char **)fw_arg1;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
43*4882a593Smuzhiyun /* ignore all built-in args if any f/w args given */
44*4882a593Smuzhiyun strcpy(arcs_cmdline, prom_argv[1]);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return 1;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
ocelot_earlyprintk_init(void)50*4882a593Smuzhiyun static void __init ocelot_earlyprintk_init(void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun void __iomem *uart_base;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun uart_base = ioremap(UART_UART, 0x20);
55*4882a593Smuzhiyun setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
ocelot_late_init(void)58*4882a593Smuzhiyun static void __init ocelot_late_init(void)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun ocelot_earlyprintk_init();
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
ocelot_fixup_fdt(const void * fdt,const void * match_data)63*4882a593Smuzhiyun static __init const void *ocelot_fixup_fdt(const void *fdt,
64*4882a593Smuzhiyun const void *match_data)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun /* This has to be done so late because ioremap needs to work */
67*4882a593Smuzhiyun late_time_init = ocelot_late_init;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return fdt;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun extern char __dtb_ocelot_pcb123_begin[];
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun MIPS_MACHINE(ocelot) = {
75*4882a593Smuzhiyun .fdt = __dtb_ocelot_pcb123_begin,
76*4882a593Smuzhiyun .fixup_fdt = ocelot_fixup_fdt,
77*4882a593Smuzhiyun .detect = ocelot_detect,
78*4882a593Smuzhiyun };
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