1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Support for Ingenic SoCs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
6*4882a593Smuzhiyun * Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org>
7*4882a593Smuzhiyun * Copyright (C) 2020 Paul Cercueil <paul@crapouillou.net>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/of_address.h>
11*4882a593Smuzhiyun #include <linux/of_fdt.h>
12*4882a593Smuzhiyun #include <linux/pm.h>
13*4882a593Smuzhiyun #include <linux/sizes.h>
14*4882a593Smuzhiyun #include <linux/suspend.h>
15*4882a593Smuzhiyun #include <linux/types.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <asm/bootinfo.h>
18*4882a593Smuzhiyun #include <asm/machine.h>
19*4882a593Smuzhiyun #include <asm/reboot.h>
20*4882a593Smuzhiyun
ingenic_get_system_type(unsigned long machtype)21*4882a593Smuzhiyun static __init char *ingenic_get_system_type(unsigned long machtype)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun switch (machtype) {
24*4882a593Smuzhiyun case MACH_INGENIC_X2000E:
25*4882a593Smuzhiyun return "X2000E";
26*4882a593Smuzhiyun case MACH_INGENIC_X2000:
27*4882a593Smuzhiyun return "X2000";
28*4882a593Smuzhiyun case MACH_INGENIC_X1830:
29*4882a593Smuzhiyun return "X1830";
30*4882a593Smuzhiyun case MACH_INGENIC_X1000E:
31*4882a593Smuzhiyun return "X1000E";
32*4882a593Smuzhiyun case MACH_INGENIC_X1000:
33*4882a593Smuzhiyun return "X1000";
34*4882a593Smuzhiyun case MACH_INGENIC_JZ4780:
35*4882a593Smuzhiyun return "JZ4780";
36*4882a593Smuzhiyun case MACH_INGENIC_JZ4775:
37*4882a593Smuzhiyun return "JZ4775";
38*4882a593Smuzhiyun case MACH_INGENIC_JZ4770:
39*4882a593Smuzhiyun return "JZ4770";
40*4882a593Smuzhiyun case MACH_INGENIC_JZ4725B:
41*4882a593Smuzhiyun return "JZ4725B";
42*4882a593Smuzhiyun default:
43*4882a593Smuzhiyun return "JZ4740";
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
ingenic_fixup_fdt(const void * fdt,const void * match_data)47*4882a593Smuzhiyun static __init const void *ingenic_fixup_fdt(const void *fdt, const void *match_data)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun * Old devicetree files for the qi,lb60 board did not have a /memory
51*4882a593Smuzhiyun * node. Hardcode the memory info here.
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun if (!fdt_node_check_compatible(fdt, 0, "qi,lb60") &&
54*4882a593Smuzhiyun fdt_path_offset(fdt, "/memory") < 0)
55*4882a593Smuzhiyun early_init_dt_add_memory_arch(0, SZ_32M);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun mips_machtype = (unsigned long)match_data;
58*4882a593Smuzhiyun system_type = ingenic_get_system_type(mips_machtype);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return fdt;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static const struct of_device_id ingenic_of_match[] __initconst = {
64*4882a593Smuzhiyun { .compatible = "ingenic,jz4740", .data = (void *)MACH_INGENIC_JZ4740 },
65*4882a593Smuzhiyun { .compatible = "ingenic,jz4725b", .data = (void *)MACH_INGENIC_JZ4725B },
66*4882a593Smuzhiyun { .compatible = "ingenic,jz4770", .data = (void *)MACH_INGENIC_JZ4770 },
67*4882a593Smuzhiyun { .compatible = "ingenic,jz4775", .data = (void *)MACH_INGENIC_JZ4775 },
68*4882a593Smuzhiyun { .compatible = "ingenic,jz4780", .data = (void *)MACH_INGENIC_JZ4780 },
69*4882a593Smuzhiyun { .compatible = "ingenic,x1000", .data = (void *)MACH_INGENIC_X1000 },
70*4882a593Smuzhiyun { .compatible = "ingenic,x1000e", .data = (void *)MACH_INGENIC_X1000E },
71*4882a593Smuzhiyun { .compatible = "ingenic,x1830", .data = (void *)MACH_INGENIC_X1830 },
72*4882a593Smuzhiyun { .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000 },
73*4882a593Smuzhiyun { .compatible = "ingenic,x2000e", .data = (void *)MACH_INGENIC_X2000E },
74*4882a593Smuzhiyun {}
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun MIPS_MACHINE(ingenic) = {
78*4882a593Smuzhiyun .matches = ingenic_of_match,
79*4882a593Smuzhiyun .fixup_fdt = ingenic_fixup_fdt,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
ingenic_wait_instr(void)82*4882a593Smuzhiyun static void ingenic_wait_instr(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun __asm__(".set push;\n"
85*4882a593Smuzhiyun ".set mips3;\n"
86*4882a593Smuzhiyun "wait;\n"
87*4882a593Smuzhiyun ".set pop;\n"
88*4882a593Smuzhiyun );
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
ingenic_halt(void)91*4882a593Smuzhiyun static void ingenic_halt(void)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun for (;;)
94*4882a593Smuzhiyun ingenic_wait_instr();
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
ingenic_pm_enter(suspend_state_t state)97*4882a593Smuzhiyun static int __maybe_unused ingenic_pm_enter(suspend_state_t state)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun ingenic_wait_instr();
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static const struct platform_suspend_ops ingenic_pm_ops __maybe_unused = {
105*4882a593Smuzhiyun .valid = suspend_valid_only_mem,
106*4882a593Smuzhiyun .enter = ingenic_pm_enter,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
ingenic_pm_init(void)109*4882a593Smuzhiyun static int __init ingenic_pm_init(void)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun if (boot_cpu_type() == CPU_XBURST) {
112*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_PM_SLEEP))
113*4882a593Smuzhiyun suspend_set_ops(&ingenic_pm_ops);
114*4882a593Smuzhiyun _machine_halt = ingenic_halt;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun return 0;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun late_initcall(ingenic_pm_init);
121