1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Cobalt time initialization. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #include <linux/i8253.h> 8*4882a593Smuzhiyun #include <linux/init.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/gt64120.h> 11*4882a593Smuzhiyun #include <asm/time.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define GT641XX_BASE_CLOCK 50000000 /* 50MHz */ 14*4882a593Smuzhiyun plat_time_init(void)15*4882a593Smuzhiyunvoid __init plat_time_init(void) 16*4882a593Smuzhiyun { 17*4882a593Smuzhiyun u32 start, end; 18*4882a593Smuzhiyun int i = HZ / 10; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun setup_pit_timer(); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun gt641xx_set_base_clock(GT641XX_BASE_CLOCK); 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * MIPS counter frequency is measured during a 100msec interval 26*4882a593Smuzhiyun * using GT64111 timer0. 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun while (!gt641xx_timer0_state()) 29*4882a593Smuzhiyun ; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun start = read_c0_count(); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun while (i--) 34*4882a593Smuzhiyun while (!gt641xx_timer0_state()) 35*4882a593Smuzhiyun ; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun end = read_c0_count(); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun mips_hpt_frequency = (end - start) * 10; 40*4882a593Smuzhiyun printk(KERN_INFO "MIPS counter frequency %dHz\n", mips_hpt_frequency); 41*4882a593Smuzhiyun } 42