1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun #include <linux/fs.h>
3*4882a593Smuzhiyun #include <linux/interrupt.h>
4*4882a593Smuzhiyun #include <asm/octeon/octeon.h>
5*4882a593Smuzhiyun #include <asm/octeon/cvmx-ciu-defs.h>
6*4882a593Smuzhiyun #include <asm/octeon/cvmx.h>
7*4882a593Smuzhiyun #include <linux/debugfs.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/seq_file.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define TIMER_NUM 3
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun static bool reset_stats;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct latency_info {
17*4882a593Smuzhiyun u64 io_interval;
18*4882a593Smuzhiyun u64 cpu_interval;
19*4882a593Smuzhiyun u64 timer_start1;
20*4882a593Smuzhiyun u64 timer_start2;
21*4882a593Smuzhiyun u64 max_latency;
22*4882a593Smuzhiyun u64 min_latency;
23*4882a593Smuzhiyun u64 latency_sum;
24*4882a593Smuzhiyun u64 average_latency;
25*4882a593Smuzhiyun u64 interrupt_cnt;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static struct latency_info li;
29*4882a593Smuzhiyun static struct dentry *dir;
30*4882a593Smuzhiyun
show_latency(struct seq_file * m,void * v)31*4882a593Smuzhiyun static int show_latency(struct seq_file *m, void *v)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun u64 cpuclk, avg, max, min;
34*4882a593Smuzhiyun struct latency_info curr_li = li;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun cpuclk = octeon_get_clock_rate();
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun max = (curr_li.max_latency * 1000000000) / cpuclk;
39*4882a593Smuzhiyun min = (curr_li.min_latency * 1000000000) / cpuclk;
40*4882a593Smuzhiyun avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun seq_printf(m, "cnt: %10lld, avg: %7lld ns, max: %7lld ns, min: %7lld ns\n",
43*4882a593Smuzhiyun curr_li.interrupt_cnt, avg, max, min);
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
oct_ilm_open(struct inode * inode,struct file * file)47*4882a593Smuzhiyun static int oct_ilm_open(struct inode *inode, struct file *file)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun return single_open(file, show_latency, NULL);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun static const struct file_operations oct_ilm_ops = {
53*4882a593Smuzhiyun .open = oct_ilm_open,
54*4882a593Smuzhiyun .read = seq_read,
55*4882a593Smuzhiyun .llseek = seq_lseek,
56*4882a593Smuzhiyun .release = single_release,
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
reset_statistics(void * data,u64 value)59*4882a593Smuzhiyun static int reset_statistics(void *data, u64 value)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun reset_stats = true;
62*4882a593Smuzhiyun return 0;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun DEFINE_SIMPLE_ATTRIBUTE(reset_statistics_ops, NULL, reset_statistics, "%llu\n");
66*4882a593Smuzhiyun
init_debugfs(void)67*4882a593Smuzhiyun static void init_debugfs(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun dir = debugfs_create_dir("oct_ilm", 0);
70*4882a593Smuzhiyun debugfs_create_file("statistics", 0222, dir, NULL, &oct_ilm_ops);
71*4882a593Smuzhiyun debugfs_create_file("reset", 0222, dir, NULL, &reset_statistics_ops);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
init_latency_info(struct latency_info * li,int startup)74*4882a593Smuzhiyun static void init_latency_info(struct latency_info *li, int startup)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun /* interval in milli seconds after which the interrupt will
77*4882a593Smuzhiyun * be triggered
78*4882a593Smuzhiyun */
79*4882a593Smuzhiyun int interval = 1;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (startup) {
82*4882a593Smuzhiyun /* Calculating by the amounts io clock and cpu clock would
83*4882a593Smuzhiyun * increment in interval amount of ms
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun li->io_interval = (octeon_get_io_clock_rate() * interval) / 1000;
86*4882a593Smuzhiyun li->cpu_interval = (octeon_get_clock_rate() * interval) / 1000;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun li->timer_start1 = 0;
89*4882a593Smuzhiyun li->timer_start2 = 0;
90*4882a593Smuzhiyun li->max_latency = 0;
91*4882a593Smuzhiyun li->min_latency = (u64)-1;
92*4882a593Smuzhiyun li->latency_sum = 0;
93*4882a593Smuzhiyun li->interrupt_cnt = 0;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun
start_timer(int timer,u64 interval)97*4882a593Smuzhiyun static void start_timer(int timer, u64 interval)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun union cvmx_ciu_timx timx;
100*4882a593Smuzhiyun unsigned long flags;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun timx.u64 = 0;
103*4882a593Smuzhiyun timx.s.one_shot = 1;
104*4882a593Smuzhiyun timx.s.len = interval;
105*4882a593Smuzhiyun raw_local_irq_save(flags);
106*4882a593Smuzhiyun li.timer_start1 = read_c0_cvmcount();
107*4882a593Smuzhiyun cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
108*4882a593Smuzhiyun /* Read it back to force wait until register is written. */
109*4882a593Smuzhiyun timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
110*4882a593Smuzhiyun li.timer_start2 = read_c0_cvmcount();
111*4882a593Smuzhiyun raw_local_irq_restore(flags);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun
cvm_oct_ciu_timer_interrupt(int cpl,void * dev_id)115*4882a593Smuzhiyun static irqreturn_t cvm_oct_ciu_timer_interrupt(int cpl, void *dev_id)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun u64 last_latency;
118*4882a593Smuzhiyun u64 last_int_cnt;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (reset_stats) {
121*4882a593Smuzhiyun init_latency_info(&li, 0);
122*4882a593Smuzhiyun reset_stats = false;
123*4882a593Smuzhiyun } else {
124*4882a593Smuzhiyun last_int_cnt = read_c0_cvmcount();
125*4882a593Smuzhiyun last_latency = last_int_cnt - (li.timer_start1 + li.cpu_interval);
126*4882a593Smuzhiyun li.interrupt_cnt++;
127*4882a593Smuzhiyun li.latency_sum += last_latency;
128*4882a593Smuzhiyun if (last_latency > li.max_latency)
129*4882a593Smuzhiyun li.max_latency = last_latency;
130*4882a593Smuzhiyun if (last_latency < li.min_latency)
131*4882a593Smuzhiyun li.min_latency = last_latency;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun start_timer(TIMER_NUM, li.io_interval);
134*4882a593Smuzhiyun return IRQ_HANDLED;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
disable_timer(int timer)137*4882a593Smuzhiyun static void disable_timer(int timer)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun union cvmx_ciu_timx timx;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun timx.s.one_shot = 0;
142*4882a593Smuzhiyun timx.s.len = 0;
143*4882a593Smuzhiyun cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
144*4882a593Smuzhiyun /* Read it back to force immediate write of timer register*/
145*4882a593Smuzhiyun timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
oct_ilm_module_init(void)148*4882a593Smuzhiyun static __init int oct_ilm_module_init(void)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun int rc;
151*4882a593Smuzhiyun int irq = OCTEON_IRQ_TIMER0 + TIMER_NUM;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun init_debugfs();
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun rc = request_irq(irq, cvm_oct_ciu_timer_interrupt, IRQF_NO_THREAD,
156*4882a593Smuzhiyun "oct_ilm", 0);
157*4882a593Smuzhiyun if (rc) {
158*4882a593Smuzhiyun WARN(1, "Could not acquire IRQ %d", irq);
159*4882a593Smuzhiyun goto err_irq;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun init_latency_info(&li, 1);
163*4882a593Smuzhiyun start_timer(TIMER_NUM, li.io_interval);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun return 0;
166*4882a593Smuzhiyun err_irq:
167*4882a593Smuzhiyun debugfs_remove_recursive(dir);
168*4882a593Smuzhiyun return rc;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
oct_ilm_module_exit(void)171*4882a593Smuzhiyun static __exit void oct_ilm_module_exit(void)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun disable_timer(TIMER_NUM);
174*4882a593Smuzhiyun debugfs_remove_recursive(dir);
175*4882a593Smuzhiyun free_irq(OCTEON_IRQ_TIMER0 + TIMER_NUM, 0);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun module_exit(oct_ilm_module_exit);
179*4882a593Smuzhiyun module_init(oct_ilm_module_init);
180*4882a593Smuzhiyun MODULE_AUTHOR("Venkat Subbiah, Cavium");
181*4882a593Smuzhiyun MODULE_DESCRIPTION("Measures interrupt latency on Octeon chips.");
182*4882a593Smuzhiyun MODULE_LICENSE("GPL");
183